HDL Verifier™ integrates with Simulink® Coder™ or Embedded Coder® to export SystemC TLM- compatible transaction-level models. You can integrate this component into your HDL simulation as a behavioral model.
The TLM generation tool provides a default socket and memory configuration. To customize the socket and memory map of the TLM component, provide an IP-XACT file. You can configure the generated component to use a SystemC thread or a callback function.
HDL Verifier generates a TLM test bench, test vectors, and a makefile to verify the component and assist with integration into your HDL simulator environment.
This example shows how to configure a Simulink® model to generate a SystemC™/TLM component using the tlmgenerator target for either Simulink Coder or Embedded Coder™.
To activate the TLM component generation options, select the system target file.
Select socket and memory map configuration for your TLM component on the TLM Mapping tab.
Define different buffering and processing behaviors for the generated TLM component
Define the timing of the TLM component input/output interface and processing thread.
Generate a standalone SystemC/TLM test bench alongside the TLM component so that you can verify the generated algorithm in the context of a TLM initiator/target pair.
Options used to generate makefiles used to compile the generated code.
How to generate your TLM component and run the optional test bench.
All IP-XACT XML files must contain information specific to MathWorks®, defined in elements within the component.
The TLM generator automatically generates an IP-XACT file that complies with IEEE® Standard for IP-XACT 1685-2009.
The System C Modeling Library (SCML) is a TLM 2.0 compatible API library for creating TLM model interfaces for use with Synopsys® prototyping tools.
After the TLM component and test bench have been generated, you can verify the generated TLM component using the test bench that was just created:
After you obtain the TLM component files generated by HDL Verifier software, you can compile the TLM component and the optional test bench with OSCI SystemC libraries and the OSCI TLM libraries.
The algorithm you use to generate the TLM component can be made of any combination of Simulink blocks that can generate C code.
The TLM generator exports a target TLM component from a Simulink model subsystem.
HDL Verifier software generates the following files:
The test bench generation option is controlled by the TLM Testbench tab of the Configuration Parameters dialog box.