Documentation

Transaction Level Model Generation

Generation of SystemC TLM virtual prototypes

HDL Verifier™ integrates with Simulink® Coder™ or Embedded Coder® to export SystemC TLM- compatible transaction-level models. You can integrate this component into your HDL simulation as a behavioral model.

The TLM generation tool provides a default socket and memory configuration. To customize the socket and memory map of the TLM component, provide an IP-XACT file. You can configure the generated component to use a SystemC thread or a callback function.

HDL Verifier generates a TLM test bench, test vectors, and a makefile to verify the component and assist with integration into your HDL simulator environment.

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