Documentation

Bus Assignment

Replace specified bus elements

  • Library:
  • Simulink / Signal Routing

Description

The Bus Assignment block assigns the values of a signal to bus elements. Use a Bus Assignment block to change bus element values without adding Bus Selector and Bus Creator blocks that select bus elements and reassemble them into a bus.

Connect the bus signal to the first input port. To other input ports, connect one or more signals whose values you want to assign to a bus element. Use the Block Parameters dialog box to specify the bus elements to be replaced. The block displays an assignment input port for each such element. For an example of a model that uses a Bus Assignment block, see Assign Signal Values to a Bus.

By default, Simulink® repairs broken selections in the Bus Assignment Block Parameters dialog boxes that are due to upstream bus hierarchy changes. Simulink generates a warning to highlight that it modified the model. To prevent Simulink from making these repairs automatically, in the Model Configuration Parameters > Diagnostics > Connectivity pane, set the Repair bus selections diagnostic to Error without repair.

Limitations

When using arrays of buses with a Bus Assignment block, these limitations apply:

  • You can assign or replace a subbus that is an array of buses. However, the nested bus cannot be nested inside an array of buses.

  • To replace a signal in an array of buses, use a Selector block to select the index for the bus element that you want to use with the Bus Assignment block. Then, use that selected bus element with the Bus Assignment block.

Ports

Input

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Input bus signals can have real or complex values of any data type supported by Simulink, including bus objects, arrays of buses, fixed-point, and enumerated data types. For details about data types, see Simulink, Data Types Supported by Simulink.

The signal connected to the assignment port must have the same structure, data type, and sample time as the bus element to which it corresponds. You can use a Rate Transition block to change the sample time of an individual signal or signals in a bus, to include the signal or bus in a nonvirtual bus. See Virtual and Nonvirtual Buses for more information.

Assignment input ports can accept signals can have real or complex values of any data type supported by Simulink, including bus objects, arrays of buses, fixed-point, and enumerated data types. You cannot use the Bus Assignment block to replace a bus that is nested within an array of buses. For details about data types, see Simulink, Data Types Supported by Simulink.

The Bus Assignment block assigns signals connected to its assignment input ports to specified elements of the bus connected to its bus input port. The block replaces the signals previously assigned to those elements. The change does not affect the composition of the bus; it affects only the values of the signals themselves. Signals not replaced are unaffected by the replacement of other signals.

Output

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Bus that includes the assigned bus element values and the values of the bus elements of the input bus that you did not assign values to.

Parameters

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List of the bus element signals of the input bus signal. An arrow next to a signal name indicates that the input signal is a bus. To display the signals in an input bus, click the arrow.

Click any item in the list to select it. To find the source of the selected signal, click Find. Simulink opens and highlights the system containing the signal source. To move the currently selected signal into the adjacent list of signals to be assigned values (see Signals that are being assigned below), click Select>>. To refresh the display to reflect modifications to the bus connected to the block, click Refresh.

Specify a search term to use for filtering a long list of input signals. Do not enclose the search term in quotation marks. The filter does a partial string search. To access filtering options, including using a regular expression for specifying the search term, click the button on the right of the Filter by name edit box.

Enable the use of MATLAB® regular expressions for filtering signal names. For example, entering t$ in the Filter by name edit box displays all signals whose names end with a lowercase t (and their immediate parents). For details, see Regular Expressions (MATLAB).

Dependencies

To access this parameter, click the button on the right of the Filter by name edit box.

By default, the list displays as a tree list of filtered signals, based on the search text in the Filter by name edit box. To use a flat list format that uses dot notation to reflect the hierarchy of bus signals, select this parameter.

Dependencies

To access this parameter, click the button on the right of the Filter by name edit box

Names of bus elements to be assigned values. This block displays an assignment input port for each bus element in this list. The label of the corresponding input port contains the name of the element. You can order the signals by using the Up, Down, or Remove. Port connectivity is maintained when you change the signal order.

If an input bus no longer contains a bus element, three question marks (???) appear before the name of that bus element The reason for this event is that the bus has changed since the last time you refreshed the Bus Assignment block input and bus element assignment lists. To address this issue, either modify the bus to include a signal of the specified name or remove the name from the list of bus elements designated to be assigned values.

Programmatic Use

Block Parameter:OutputSignals
Type:character vector
Values: 'signal1'|'signal2'
Default:none

Block Characteristics

Data Types

double | single | Boolean | base integer | fixed point | enumerated | bus

Multidimensional Signals

Yes

Variable-Size Signals

Yes

Extended Capabilities

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Introduced before R2006a

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