Tapped Delay

Delay scalar signal multiple sample periods and output all delayed versions

• Library:

• Simulink / Discrete

  HDL Coder / Discrete

Description

The Tapped Delay block delays an input by the specified number of sample periods and outputs all the delayed versions. Use this block to discretize a signal in time or resample a signal at a different rate.

The block accepts one scalar input and generates an output vector that contains each delay. Specify the order of the delays in the output vector with the Order output vector starting with parameter:

• Oldest orders the output vector starting with the oldest delay version and ending with the newest delay version.

• Newest orders the output vector starting with the newest delay version and ending with the oldest delay version.

Specify the output vector for the first sampling period with the Initial condition parameter. Careful selection of this parameter can minimize unwanted output behavior.

Specify the time between samples with the Sample time parameter. Specify the number of delays with the Number of delays parameter. A value of -1 instructs the block to inherit the number of delays by backpropagation. Each delay is equivalent to the z^-1 discrete-time operator, which the Unit Delay block represents.

Ports

Input

Port_1 — Input signal

scalar

Input signal to delay, specified as a scalar.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point

Output

Port_1 — Delayed versions of input signal

scalar | vector

Output signal is all delayed versions of the input signal. Use the Order output vector starting with parameter to specify the order of delayed signals in the output vector.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point

Parameters

Initial condition — Initial output

0.0 (default) | scalar | vector | matrix

Specify the initial output of the simulation. The Initial condition parameter is converted from a double to the input data type offline using round-to-nearest and saturation.

Limitations

The initial condition of this block cannot be inf or NaN.

Programmatic Use

Block Parameter: vinit

Type: character vector

Values: scalar | vector | matrix

Default: '0.0'

Sample time — Time between samples

-1 (default) | scalar | vector

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. For more information, see Specify Sample Time.

Programmatic Use

Block Parameter: samptime

Type: character vector

Values: scalar | vector

Default: '-1'

Number of delays — Number of discrete-time operators

4 (default) | positive scalar | -1 (for inherited)

Specify the number of discrete-time operators as a positive scalar, or -1 for inherited.

Programmatic Use

Block Parameter: NumDelays

Type: character vector

Values: positive scalar | -1 (inherited)

Default: '4'

Order output vector starting with — Order of output

Oldest (default) | Newest

Specify whether to output the oldest delay version first, or the newest delay version first.

Programmatic Use

Block Parameter: DelayOrder

Type: character vector

Values: 'Oldest' | 'Newest'

Default: 'Oldest'

Include current input in output vector — Include current input in output vector

off (default) | on

Select this check box to include the current input in the output vector.

Programmatic Use

Block Parameter: includeCurrent

Type: character vector

Values: 'off' | 'on'

Default: 'off'

Model Examples

Fixed-Point S-Functions: Product and Sum

How to exercise a custom C language S-function written to compute a fixed-point "product and sum" operation. To see the source code for the S-function, use the right-click context menu to select "Block Parameters". When the dialog box appears, press the Edit button.

Open Model

Internet Low Bitrate Codec (iLBC) for VoIP

Implements the Internet Low Bitrate Codec (iLBC) and illustrates its use. iLBC is designed for encoding and decoding speech for transmission via VoIP (Voice Over Internet Protocol).

Open Model

Block Characteristics

Data Types	Boolean | double | fixed point | integer | single
Direct Feedthrough	no
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

For more information about HDL code generation, see Tapped Delay.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Convert floating-point algorithms to fixed point using Fixed-Point Designer™.