Delay signal one sample period, with external initial condition
The Unit Delay External IC block delays its input by one sample period. This block is equivalent to the z-1 discrete-time operator. The block accepts one input and generates one output, both of which can be scalar or vector. If the input is a vector, all elements of the vector are delayed by the same sample period.
The block's output for the first sample period is equal to the signal IC.
You specify the time between samples with the Sample time parameter. A setting of -1 means that the block inherits the Sample time.
The Unit Delay External IC block accepts signals of the following data types:
The data types of the inputs u and IC must be the same. The output has the same data type as u and IC.
For more information, see Data Types Supported by Simulink in the Simulink® documentation.
Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time in the online documentation for more information.
No, of the input port
Yes, of the external IC port
Specified in the Sample time parameter
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