While Iterator Subsystem

Represent subsystem that executes repeatedly while condition is satisfied during simulation time step


Ports & Subsystems


The While Iterator Subsystem block is a Subsystem block that is preconfigured to serve as a starting point for creating a subsystem that executes repeatedly while a condition is satisfied during a simulation time step.

See the While Iterator block and Use Control Flow Logic for more information.

When using simplified initialization mode, you cannot place any block needing elapsed time within an Iterator Subsystem. In simplified initialization mode, Iterator subsystems do not maintain elapsed time, so Simulink will report an error if any such block (such as the Discrete-Time Integrator block) is placed within the subsystem. For more information on simplified initialization modes, see Underspecified initialization detection.


Data Types

Double | Single | Boolean | Base Integer | Fixed-Point | Enumerated | Bus

Multidimensional Signals


Variable-Size Signals


Code Generation


Introduced before R2006a

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