Zero-Order Hold

Implement zero-order hold of one sample period




The Zero-Order Hold block holds its input for the sample period you specify. The block accepts one input and generates one output. Each signal can be scalar or vector. If the input is a vector, the block holds all elements of the vector for the same sample period.

You specify the time between samples with the Sample time parameter. A setting of -1 means the block inherits the Sample time.

    Tip   Do not use the Zero-Order Hold block to create a fast-to-slow transition between blocks operating at different sample rates. Instead, use the Rate Transition block.

Comparison with Similar Blocks

Blocks with Similar Functionality

The Unit Delay, Memory, and Zero-Order Hold blocks provide similar functionality but have different capabilities. Also, the purpose of each block is different. The sections that follow highlight some of these differences.

Recommended Usage for Each Block

BlockPurpose of the BlockReference Examples
Unit DelayImplement a delay using a discrete sample time that you specify. Ideally, the block accepts and outputs signals with a discrete sample time.
MemoryImplement a delay by one major integration time step. Ideally, the block accepts continuous (or fixed in minor time step) signals and outputs a signal that is fixed in minor time step.
Zero-Order HoldConvert an input signal with a continuous sample time to an output signal with a discrete sample time.

Overview of Block Capabilities

Unit DelayMemoryZero-Order Hold
Specification of initial conditionYesYesNo, because the block output at time t = 0 must match the input value.
Specification of sample timeYesNo, because the block can only inherit sample time (from the driving block or the solver used for the entire model).Yes
Support for frame-based signalsYesNo Yes
Support for state loggingYesNoNo

Effect of Solver Specification on Block Output

When you specify a discrete sample time in the dialog box for a Unit Delay or Zero-Order Hold block, the block output can differ depending on the solver specification for the model.

Suppose that you have a modelmodel with Unit Delay and Zero-Order Hold blocks, which both use a discrete sample time of 1:

The Repeating Sequence Stair block uses a continuous sample time of 0 to provide input signals to the Unit Delay and Zero-Order Hold blocks.

If the model uses a fixed-step solver with a step size of 1, the scope shows the following simulation results:

If the model uses a variable-step solver, the scope shows the following simulation results:

The Zero-Order Hold block takes the input value of the Repeating Sequence Stair block at t = 0, 1, 2, ... , 9 and holds each input value for a sample period (1 second). The Unit Delay block applies the same 1-second hold to each input value of the Repeating Sequence Stair block, but also delays each value by a sample period. The Initial conditions parameter specifies the output for the Unit Delay block during the first sample period. For more information about sample time, see What Is Sample Time? and Specify Sample Time.

Solver specification for a model also affects the behavior of the Memory block. For details, see Examples of Memory Block Usage.

Data Type Support

The Zero-Order Hold block accepts real or complex signals of any data type that Simulink® supports, including fixed-point and enumerated data types.

For more information, see Data Types Supported by Simulink in the Simulink documentation.

Parameters and Dialog Box

Sample time (-1 for inherited)

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time in the online documentation for more information.

Do not specify a continuous sample time, either 0 or [0,0]. This block supports only discrete sample times. When this parameter is -1, the inherited sample time must be discrete and not continuous.

Bus Support

The Zero-Order Hold block is a bus-capable block. The input can be a virtual or nonvirtual bus signal. No block-specific restrictions exist. All signals in a nonvirtual bus input to a Zero-Order Hold block must have the same sample time, even if the elements of the associated bus object specify inherited sample times. You can use a Rate Transition block to change the sample time of an individual signal, or of all signals in a bus. See Composite Signals and Bus-Capable Blocks for more information.

You can use an array of buses as an input signal to a Zero-Order Hold block. For details about defining and using an array of buses, see Combine Buses into an Array of Buses.


The following models show how to use the Zero-Order Hold block:




Direct Feedthrough


Sample Time

Specified in the Sample time parameter

Scalar Expansion




Zero-Crossing Detection


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