What Is Design Error Detection?

Explains the design error detection analysis option.

Dead Logic Detection

Describes the two analysis modes for dead logic detection in Simulink^® Design Verifier™.

Model Objects That Receive Dead Logic Detection

Information about dead logic design error detection for specific model objects.

Common Causes for Dead Logic

Describes several scenarios that results in dead logic.

Analyzing the Results for a Dead Logic Analysis

This example demonstrates how to isolate potential causes of dead logic using the sldvexCommonCausesOfDeadLogic model.

Detect Dead Logic Caused by an Incorrect Value

Example showing how to find an incorrect input specification using a dead logic result.

Design Verifier Pane: Design Error Detection

Specify options that control how Simulink Design Verifier detects runtime errors in the models it analyzes.

Simulink Design Verifier Options

Overview of the Simulink Design Verifier options in the Configuration Parameters dialog box.

Simulink Design Verifier Reports

Describes the different parts of a Simulink Design Verifier report.

Simulink Design Verifier Data Files

Describes the contents of a Simulink Design Verifier data file.