SoC Blockset™ enables simulation and evaluation of shared memory transactions in Simulink®. To include a memory system in your SoC model, configure a memory controller for the desired number of memory channels, and then connect the controller to memory channel blocks for arbitrating and handling memory traffic.
|Memory Channel||Stream data through a memory channel|
|Memory Controller||Arbitrate memory transactions for one or more Memory Channel blocks|
|Memory Traffic Generator||Generate traffic towards memory controller|
|Register Channel||Timing model for transfer of register values|
|IP Core Register Read||Model register writes from software to hardware|
|Interrupt Channel||Send interrupt to processor from hardware|
|SoC Bus Selector||Convert bus to control signals|
|SoC Bus Creator||Convert control signals to bus|
|Stream FIFO||Control backpressure between hardware logic and upstream data interface|
|Video Stream FIFO||Control backpressure between hardware logic and upstream video interface|
|Stream Connector||Connect two IPs with data streaming interfaces|
|Video Stream Connector||Connect two IPs with video streaming interfaces|
Introduction to memory and register transfers.
Supported memory channel protocols and control signals.
How to design your model for AXI4-Stream vector or scalar interface generation.
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
How to design your model for IP core generation with AXI4-stream video interfaces.