HDL Coder™ Support Package for Intel® FPGA Boards enables IP core generation and FPGA turnkey workflows for programming supported Intel FPGAs and SoC FPGAs. The IP core generation and FPGA turnkey workflows help you map your algorithm I/O to onboard interfaces, generate HDL code, and synthesize the generated code. HDL Coder also provides integration with Intel Quartus® to synthesize the generated code into a bitstream that you can directly download on to Intel FPGA development boards.
Setup and install the support package for use with supported third-party tools and hardware
Learn about the hardware-software co-design workflow and how to use the Workflow Advisor to run the algorithm on an FPGA board.
Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board.
Define and register custom reference design or custom board for Intel FPGA.
Create bitstream containing user programming and download it to the FPGA processor chip