Documentation

HDL Coder Support Package for Intel SoC Devices

Generate code for the FPGA portion of the Intel SoC FPGA

HDL Coder™ Support Package for Intel® SoC Devices supports the generation of IP cores that can be integrated into FPGA designs using Intel Qsys. When used in combination with the Embedded Coder® Support Package for Intel SoC Devices, this solution can program the Intel SoC FPGA using C and HDL code generation. The hardware/software codesign workflow spans simulation, prototyping, verification, and implementation.

Setup and Configuration

Download and install support package for use with third-party EDA tools and supported hardware

Getting Started

Learn about the hardware-software co-design workflow and how to use the Workflow Advisor to run the algorithm on the SoC platform

Custom IP Core Generation

Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board

Custom Board and Reference Design

Define and register custom reference design or custom board for Intel SoC device

Deployment

Create bitstream containing user programming and download it to Intel SoC platform