Main Content

CLB X-BAR

The CLB X-BAR brings signals to the CLB modules. The CLB X-BAR has eight outputs which are routed to each CLB module.

AUXSIG# MUX select

Select the MUX to map the signal to the MUX AUXSIG#. AUXSIG# (# can take values 0 to 7)

You can select up to one signal per mux (maximum available up to of 31 muxes) for each AUXSIG# output. AUXSIG# MUX select values are based on the processor selected.

Selecting Disable all will indicate that all MUXes are disabled and the CLB X-BAR# is not configured.

Note

AUXSIG# MUX select will not have MUX entries whose inputs are all reserved.

Select MUX input

Select the signal to the MUX selected in AUXSIG# MUX select. Ensure the selected MUX input peripheral is enabled and utilized.

Select the input signals for the MUX which is sent to the CLB. You can select one signal per MUX. The input signal to the MUX varies based on the MUX selected and processor.

The following table lists the AUXSIG# MUX select and Select MUX input for C28x processor F2838x. The row headers 0-3 represent the Select MUX input and column headers 0-31 represent the AUXSIG# MUX select.

CLB X-BAR Mux Configuration Table - F2838x

Select MUX INPUT 0123
AUXSIG# MUX select
0CMPSS1.CTRIPHCMPSS1.CTRIPH_OR_CTRIPADCAEVT1ECAP1.OUT
1CMPSS1.CTRIPLINPUTXBAR1CLB1_OUT4ADCCEVT1
2CMPSS2.CTRIPHCMPSS2.CTRIPH_OR_CTRIPADCAEVT2ECAP2.OUT
3CMPSS2.CTRIPLINPUTXBAR2CLB1_OUT5ADCCEVT2
4CMPSS3.CTRIPHCMPSS3.CTRIPH_OR_CTRIPADCAEVT3ECAP3.OUT
5CMPSS3.CTRIPLINPUTXBAR3CLB2_OUT4ADCCEVT3
6CMPSS4.CTRIPHCMPSS4.CTRIPH_OR_CTRIPADCAEVT4ECAP4.OUT
7CMPSS4.CTRIPLINPUTXBAR4CLB2_OUT5ADCCEVT4
8CMPSS5.CTRIPHCMPSS5.CTRIPH_OR_CTRIPADCBEVT1ECAP5.OUT
9CMPSS5.CTRIPLINPUTXBAR5CLB3_OUT4ADCDEVT1
10CMPSS6.CTRIPHCMPSS6.CTRIPH_OR_CTRIPADCBEVT2ECAP6.OUT
11CMPSS6.CTRIPLINPUTXBAR6CLB3_OUT5ADCDEVT2
12CMPSS7.CTRIPHCMPSS7.CTRIPH_OR_CTRIPADCBEVT3ECAP7.OUT
13CMPSS7.CTRIPLADCSOCACLB4_OUT4ADCDEVT3
14CMPSS8.CTRIPHCMPSS7.CTRIPH_OR_CTRIPADCBEVT4EXTSYNCOUT
15CMPSS8.CTRIPLADCSOCBCLB4_OUT5ADCDEVT4
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_ COMPLSD1FLT1.COMPZSD1FLT1.DRINT
17SD1FLT1.COMPLINPUTXBAR7CLB5_OUT4CPU1.CLA1HALT
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_ COMPLSD1FLT2.COMPZSD1FLT2.DRINT
19SD1FLT2.COMPLINPUTXBAR8CLB5_OUT5Reserved
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_ COMPLSD1FLT3.COMPZSD1FLT3.DRINT
21SD1FLT3.COMPLINPUTXBAR9CLB6_OUT4Reserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_ COMPLSD1FLT4.COMPZSD1FLT4.DRINT
23SD1FLT4.COMPLINPUTXBAR10CLB6_OUT5EMAC.PPS1
24SD2FLT1.COMPHSD2FLT1.COMPH_OR_ COMPLSD2FLT1.COMPZSD2FLT1.DRINT
25SD2FLT1.COMPLINPUTXBAR11MCANA.FEVT0CLB7_OUT4
26SD2FLT2.COMPHSD2FLT2.COMPH_OR_ COMPLSD2FLT2.COMPZSD2FLT2.DRINT
27SD2FLT2.COMPLINPUTXBAR12MCANA.FEVT1CLB7_OUT5
28SD2FLT3.COMPHSD2FLT3.COMPH_OR_ COMPLSD2FLT3.COMPZSD2FLT3.DRINT
29SD2FLT3.COMPLINPUTXBAR13MCANA.FEVT2CLB8_OUT4
30SD2FLT4.COMPHSD2FLT4.COMPH_OR_ COMPLSD2FLT4.COMPZSD2FLT4.DRINT
31SD2FLT4.COMPLINPUTXBAR14EMAC.PPS0CLB8_OUT5

CLB X-BAR Mux Configuration Table - F28003x

Select MUX INPUT 0123
AUXSIG# MUX select
0CMPSS1.CTRIPHCMPSS1.CTRIPH_OR_CTRIPADCAEVT1ECAP1.OUT
1CMPSS1.CTRIPLINPUTXBAR1CLB1_OUT4ADCCEVT1
2CMPSS2.CTRIPHCMPSS2.CTRIPH_OR_CTRIPADCAEVT2ECAP2.OUT
3CMPSS2.CTRIPLINPUTXBAR2CLB1_OUT5ADCCEVT2
4CMPSS3.CTRIPHCMPSS3.CTRIPH_OR_CTRIPADCAEVT3ECAP3.OUT
5CMPSS3.CTRIPLINPUTXBAR3CLB2_OUT4ADCCEVT3
6CMPSS4.CTRIPHCMPSS4.CTRIPH_OR_CTRIPADCAEVT4ECAP4.OUT
7CMPSS4.CTRIPLINPUTXBAR4CLB2_OUT5ADCCEVT4
8ReservedReservedADCBEVT1Reserved
9ReservedINPUTXBAR5CLB3_OUT4Reserved
10ReservedReservedADCBEVT2Reserved
11ReservedINPUTXBAR6CLB3_OUT5Reserved
12ReservedReservedADCBEVT3Reserved
13ReservedADCSOCAOCLB4_4Reserved
14ReservedReservedADCBEVT4EXTSYNCOUT
15ReservedADCSOCBOCLB4_5Reserved
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_ COMPLSD1FLT1.COMPZSD1FLT1.DRINT
17SD1FLT1.COMPLINPUTXBAR7ReservedCPU1.CLA1HALT
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_ COMPLSD1FLT2.COMPZSD1FLT2.DRINT
19SD1FLT2.COMPLINPUTXBAR8ReservedERRORSTS ERROR
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_ COMPLSD1FLT3.COMPZSD1FLT3.DRINT
21SD1FLT3.COMPLINPUTXBAR9ReservedReserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_ COMPLSD1FLT4.COMPZSD1FLT4.DRINT
23SD1FLT4.COMPLINPUTXBAR10ReservedReserved
24SD2FLT1.COMPHSD2FLT1.COMPH_OR_ COMPLSD2FLT1.COMPZSD2FLT1.DRINT
25SD2FLT1.COMPLINPUTXBAR11MCANA.FEVT0Reserved
26SD2FLT2.COMPHSD2FLT2.COMPH_OR_ COMPLSD2FLT2.COMPZSD2FLT2.DRINT
27SD2FLT2.COMPLINPUTXBAR12MCANA.FEVT1Reserved
28SD2FLT3.COMPHSD2FLT3.COMPH_OR_ COMPLSD2FLT3.COMPZSD2FLT3.DRINT
29SD2FLT3.COMPLINPUTXBAR13MCANA.FEVT2Reserved
30SD2FLT4.COMPHSD2FLT4.COMPH_OR_ COMPLSD2FLT4.COMPZSD2FLT4.DRINT
31SD2FLT4.COMPLINPUTXBAR14ERRORSTS ERRORReserved

CLB X-BAR Mux Configuration Table - F28004x

Select MUX INPUT0123
AUXSIG# MUX select
0CMPSS1.CTRIPOUTHCMPSS1.CTRIPOUTH_OR_CTRIPOUTLADCAEVT1ECAP1OUT
1CMPSS1.CTRIPOUTLINPUTXBAR1CLB1_OUT4ADCCEVT1
2CMPSS2.CTRIPOUTHCMPSS2.CTRIPOUTH_OR_CTRIPOUTLADCAEVT2ECAP2OUT
3CMPSS2.CTRIPOUTLINPUTXBAR2CLB1_OUT5ADCCEVT2
4CMPSS3.CTRIPOUTHCMPSS3.CTRIPOUTH_OR_CTRIPOUTLADCAEVT3ECAP3OUT
5CMPSS3.CTRIPOUTLINPUTXBAR3CLB2_OUT4ADCCEVT3
6CMPSS4.CTRIPOUTHCMPSS4.CTRIPOUTH_OR_CTRIPOUTLADCAEVT4ECAP4OUT
7CMPSS4.CTRIPOUTLINPUTXBAR4CLB2_OUT5ADCCEVT4
8CMPSS5.CTRIPOUTHCMPSS5.CTRIPOUTH_OR_CTRIPOUTLADCBEVT1ECAP5OUT
9CMPSS5.CTRIPOUTLINPUTXBAR5CLB3_OUT4Reserved
10CMPSS6.CTRIPOUTHCMPSS6.CTRIPOUTH_OR_CTRIPOUTLADCBEVT2ECAP6OUT
11CMPSS6.CTRIPOUTLINPUTXBAR6CLB3_OUT5Reserved
12CMPSS7.CTRIPOUTHCMPSS7.CTRIPOUTH_OR_CTRIPOUTLADCBEVT3ECAP7OUT
13CMPSS7.CTRIPOUTLADCSOCAOCLB4_OUT4Reserved
14ReservedReservedADCBEVT4EXTSYNCOUT
15ReservedADCSOCBOCLB4_OUT5Reserved
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_COMPLReservedReserved
17SD1FLT1.COMPLReservedReservedCLAHALT
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_COMPLReservedReserved
19SD1FLT2.COMPLReservedReservedReserved
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_COMPLReservedReserved
21SD1FLT3.COMPLReservedReservedReserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_COMPLReservedReserved
23SD1FLT4.COMPLReservedReservedReserved

CLB X-BAR Mux Configuration Table - F28002x

Select MUX INPUT0123
AUXSIG# MUX select
0CMPSS1.CTRIPOUTHCMPSS1.CTRIPOUTH_OR_CTRIPOUTLADCAEVT1ECAP1OUT
1CMPSS1.CTRIPOUTLINPUTXBAR1CLB1_OUT4ADCCEVT1
2CMPSS2.CTRIPOUTHCMPSS2.CTRIPOUTH_OR_CTRIPOUTLADCAEVT2ECAP2OUT
3CMPSS2.CTRIPOUTLINPUTXBAR2CLB1_OUT5ADCCEVT2
4CMPSS3.CTRIPOUTHCMPSS3.CTRIPOUTH_OR_CTRIPOUTLADCAEVT3ECAP3OUT
5CMPSS3.CTRIPOUTLINPUTXBAR3CLB2_OUT4ADCCEVT3
6CMPSS4.CTRIPOUTHCMPSS4.CTRIPOUTH_OR_CTRIPOUTLADCAEVT4Reserved
7CMPSS4.CTRIPOUTLINPUTXBAR4CLB2_OUT5ADCCEVT4
9ReservedINPUTXBAR5ReservedReserved
11ReservedINPUTXBAR6ReservedReserved
13ReservedADCSOCAOReservedReserved
14ReservedReservedReservedEXTSYNCOUT

CLB X-BAR Mux Configuration Table - F2807x/F2837xS/F2837xD

Select MUX INPUT0123
AUXSIG# MUX select
0CMPSS1.CTRIPH

CMPSS1.CTRIPH_OR_CTRIPL

ADCAEVT1ECAP1.OUT
1CMPSS1.CTRIPLINPUTXBAR1CLB1_OUT4ADCCEVT1
2CMPSS2.CTRIPH

CMPSS2.CTRIPH_OR_CTRIPL

ADCAEVT2ECAP2.OUT
3CMPSS2.CTRIPLINPUTXBAR2CLB1_OUT5ADCCEVT2
4CMPSS3.CTRIPH

CMPSS3.CTRIPH_OR_CTRIPL

ADCAEVT3ECAP3OUT
5CMPSS3.CTRIPLINPUTXBAR3CLB2_OUT4ADCCEVT3
6CMPSS4.CTRIPH

CMPSS4.CTRIPH_OR_CTRIPL

ADCAEVT4ECAP4.OUT
7CMPSS4.CTRIPLINPUTXBAR4CLB2_OUT5ADCCEVT4
8CMPSS5.CTRIPH

CMPSS4.CTRIPH_OR_CTRIPL

ADCBEVT1ECAP5.OUT
9CMPSS5.CTRIPLINPUTXBAR5CLB3_OUT4ADCCEVT1
10CMPSS6.CTRIPH

CMPSS4.CTRIPH_OR_CTRIPL

ADCBEVT1ECAP6.OUT
11CMPSS6.CTRIPLINPUTXBAR6CLB3_OUT5ADCCEVT2
12CMPSS7.CTRIPH

CMPSS7.CTRIPH_OR_CTRIPL

ADCBEVT3Reserved
13CMPSS7.CTRIPLADCSOCAOCLB4_OUT4ADCDEVT3
14CMPSS8.CTRIPH

CMPSS8.CTRIPH_OR_CTRIPL

ADCBEVT4EXTSYNCOUT
15CMPSS8.CTRIPLADCSOCBCLB4_OUT5ADCDEVT4
16SD1FLT1.COMPH

SD1FLT1.COMPH_OR_COMPL

ReservedReserved
17SD1FLT1.COMPLReservedReservedReserved
18SD1FLT2.COMPH

SD1FLT2.COMPH_OR_COMPL

ReservedReserved
19SD1FLT2.COMPLReservedReservedReserved
20SD1FLT3.COMPH

SD1FLT3.COMPH_OR_COMPL

ReservedReserved
21SD1FLT3.COMPLReservedReservedReserved
22SD1FLT4.COMPH

SD1FLT4.COMPH_OR_COMPL

ReservedReserved
23SD1FLT4.COMPLReservedReservedReserved
24SD2FLT1.COMPH

SD2FLT1.COMPH_OR_COMPL

ReservedReserved
25SD2FLT1.COMPLReservedReservedReserved
26SD2FLT2.COMPH

SD2FLT2.COMPH_OR_COMPL

ReservedReserved
27SD2FLT2.COMPLReservedReservedReserved
28SD2FLT3.COMPH

SD2FLT3.COMPH_OR_COMPL

ReservedReserved
29SD2FLT3.COMPLReservedReservedReserved
30SD2FLT4.COMPH

SD2FLT4.COMPH_OR_COMPL

ReservedReserved
31SD2FLT4.COMPLReservedReservedReserved

For F2837x and F2807x processors CLB clock comes from ePWM clock. And for F2837xD, if both CLB and ePWM are used then they should be in same CPU.

AUXSIG# MUX (MUX 0 -> 31)

Indicates the input signal selected for each output# MUX. For example, XXXX1XXXXXXXXXXXXXXXXXXXXXXXXXX indicates that input signal 1 was selected for MUX 4. X indicates that the MUX is disabled and no signal from the MUX will be sent to the CLB X-BAR.

All the signals which are selected will be logically OR'd before being passed on to the respective AUXSIG#x signal on the CLB.

RESET AUXSIG# MUX

Resets the signal selection for the MUX done so far.

Resets the AUXSIG# MUX (MUX 0->31) and Select MUX input inputs.

Invert AUXSIG#

Select to invert the auxiliary signal on the CLB.

Related Topics