The configurable logic block (CLB) is a collection of configurable blocks that can be inter-connected using software to implement custom digital logic functions. The CLB is able to enhance existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules (eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to perform small logical functions such as simple PWM generators, or to implement custom serial data exchange protocols.
For F2838x processor the CLB tile clock is configured in SYNC mode and is derived as SYSCLKOUT/EPWMCLKDIV (Achievable SYSCLKOUT in MHz/EPWM clock divider) should be always less than 150MHz.
For F28002x and F28004x processors the CLB tile clock is configured in SYNC mode and should be less than 100 MHz.
For F2837x and F2807x processors CLB clock comes from ePWM clock. And for F2837xD, if both CLB and ePWM are used then they should be in same CPU.
- Enable CLB Tile #
Select this option to enable the CLB tile. The number of CLB tile available based on the hardware board.
This option will enable you to configure the input and output signals to the CLB tile, the logic for the CLB tile can be implemented in TI Code Composer Studio CLB tool with system configuration file and the generated clb_config.h and clb_config.c file can be integrated with the parameters CLB configuration header file (clb_config.h) and CLB configuration source file (clb_congif.c).
- Tile # Name
Specify the tile name. Ensure that the tile name is same as the name mentioned in the CLB Tool.
Add the tile# name for the given CLB tile. This tile name will be used to generate the required function declaration and calling the function for CLB tile configuration. The tile names entered here should be an exact match with the tile name set in CLB tool system configuration file In TI CCS used to generate the clb_config.c and clb_config.h file. Mismatch may result in build failure or in incorrect configuration of CLB tiles. For example, if the tile name is TILE1, the function present in clb_config.c and clb_config.h is initTILE1 and the function called during code generation is also initTILE1.
- IN# mux selection
Configure the signal source type for the IN# mux for CLB# tile. The # corresponds to the values 0 to 7. The type of signal can be global inputs, local inputs and GPREG.
Ensure corresponding X-BAR configurations are done to route the signals properly for the CLB tile inputs
Configure the peripheral signal as input to the CLB tile. Depending upon the signal type selected for IN# mux selection, different input signals can be configured. For GPREG IN# mux selection, the input values can be either 0 or 1.
- Input filtering
Configure the type of input filtering for the signal type Global inputs and Local inputs. This option will be disabled for GPREG as it is not applicable. The values can be No filtering, Rising edge detect, falling edge detect and any edge detect.
- Enable sync
Configure the synchronization option (SYNC) for the Global inputs and Local inputs IN# mux selection only. Enabling this option will synchronize the signal with respective to clock. This option is not applicable for GPREG type and will be disabled for the same.
For the signals which are specified as ASYNC in TI reference manuals, the input filter synchronizer must be enabled explicitly.
- Route OUT# signal to
Use this option to route the CLB output signal to the peripheral instead of the default peripheral signal. Each CLB output signal passes through an external multiplexer that intersects a specific peripheral signal. If the options in this parameter is enabled it will route the CLB output for the specific peripheral instead of the original peripheral signal.
Each output signal will be replicated and can be routed to different peripheral.
1) In TI F2838x (C28x) and TI F28002x, for CLB tile1 Out0 is replicated as Out0_0, Out0_1 (also represented as Out8), Out0_2 (also represented as Out16) and Out0_3 (also represented as Out24). Out0_0 is routed to ePWM1A, OUT0_1 is routed to eQEP.QCLK, Out0_2 is routed to Global mux and Out0_3 is routed to SPI_A.CLKIN. So same output signal is routed to 4 different peripherals.
2) In TI Piccolo F28004x, for CLB tile1 Out0 is replicated as Out0_0, Out0_1 (also represented as Out8), Out0_2 (also represented as Out16) and Out0_3 (also represented as Out24). Out0_0 is routed to ePWM1A, OUT0_1 is routed to eQEP.QCLK, Out0_2 is routed to Global mux. So same output signal can be routed to 3 peripherals.
Similarly all the out# signals are replicated. these options are provided as check boxes with respective to the peripheral points where the CLB output signals are used as replacement to original peripheral signal.
Global Mux option refers to the Global Input signal mux to each CLB Tile.
- CLB configuration header file (clb_config.h)
Provide the paths for the CLB configuration header file clb_config.h. This file holds the required function declarations and headers used to configure the CLB tile. This can be generated using system configuration in CLB tool using TI Code composer studio. Ensure the tile names selected in CLB tool matches with the tile name provided in the parameter Tile# name.
You can provide the file path relative to the model path.
- CLB configuration source file (clb_config.c)
Provide the paths for the CLB configuration source file clb_config.c. This file holds the required function definitions used to configure the CLB tile. This can be generated using system configuration in CLB tool using TI Code composer studio. Ensure the tile names selected in CLB tool matches with the tile name provided in the parameter Tile# name.
You can provide the file path relative to the model path.
Click this button to browse the path for the file selection.
Click this button to open the existing file for editing in MATLAB® editor.