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Output X-BAR

The crossbars (X-BARs) provides flexibility to connect device inputs, outputs, and internal resources in a variety of configurations using Input X-BAR, Output X-BAR, and ePWM X-BAR.

Output X-BAR takes signals from inside the device and brings them out to a GPIO. The Output X-BAR contains eight outputs. The signals which is passed to the GPIO comes from the Multiplexer(MUX). Each output has 32 MUX and you can select one signal per MUX.

OUPUT# MUX select

Select the MUX to map the signal to the MUX output. OUTPUT# MUX select value ranges based on the processor selected.

Selecting Disable all will indicate that all MUXes are disabled and the Output X-BAR# is not configured.

Note

OUTPUT# MUX select will not have MUX entries whose inputs are all reserved.

Select MUX input

Select the signal to the MUX selected in OUTPUT# MUX select.

Select the input signals for the MUX which is sent to the GPIO. You can select one signal per MUX. The input signal to the MUX varies based on the MUX selected and processor.

The following table lists the OUTPUT MUX select and Select MUX input for C28x processor F2838x. The row headers 0-3 represent the Select MUX input and column headers 0-31 represent the OUTPUT MUX select.

Output X-BAR Mux Configuration Table - F2838x

Select MUX INPUT 0123
OUTPUT# MUX select
0CMPSS1.CTRIPOUTHCMPSS1.CTRIPOUTH_OR_ CTRIPOUTLADCAEVT1ECAP1.OUT
1CMPSS1.CTRIPOUTLINPUTXBAR1CLB1_4.1ADCCEVT1
2CMPSS2.CTRIPOUTHCMPSS2.CTRIPOUTH_OR_ CTRIPOUTLADCAEVT2ECAP2.OUT
3CMPSS2.CTRIPOUTLINPUTXBAR2CLB1_5.1ADCCEVT2
4CMPSS3.CTRIPOUTHCMPSS3.CTRIPOUTH_OR_ CTRIPOUTLADCAEVT3ECAP3.OUT
5CMPSS3.CTRIPOUTLINPUTXBAR3CLB2_4.1ADCCEVT3
6CMPSS4.CTRIPOUTHCMPSS4.CTRIPOUTH_OR_ CTRIPOUTLADCAEVT4ECAP4.OUT
7CMPSS4.CTRIPOUTLINPUTXBAR4CLB2_5.1ADCCEVT4
8CMPSS5.CTRIPOUTHCMPSS5.CTRIPOUTH_OR_ CTRIPOUTLADCBEVT1ECAP5.OUT
9CMPSS5.CTRIPOUTLINPUTXBAR5CLB3_4.1ADCDEVT1
10CMPSS6.CTRIPOUTHCMPSS6.CTRIPOUTH_OR_ CTRIPOUTLADCBEVT2ECAP6.OUT
11CMPSS6.CTRIPOUTLINPUTXBAR6CLB3_5.1ADCDEVT2
12CMPSS7.CTRIPOUTHCMPSS7.CTRIPOUTH_OR_ CTRIPOUTLADCBEVT3ECAP7.OUT
13CMPSS7.CTRIPOUTLADCSOCACLB4_4.1ADCDEVT3
14CMPSS8.CTRIPOUTHCMPSS8.CTRIPOUTH_OR_ CTRIPOUTLADCBEVT4EXTSYNCOUT
15CMPSS8.CTRIPOUTLADCSOCBCLB4_5.1ADCDEVT4
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_ COMPLReservedReserved
17SD1FLT1.COMPLReservedCLB5_4.1CPU1.CLA1HALT
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_ COMPLReservedECATSYNC0
19SD1FLT2.COMPLReservedCLB5_5.1ECATSYNC1
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_ COMPLReservedReserved
21SD1FLT3.COMPLReservedCLB6_4.1Reserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_ COMPLReservedReserved
23SD1FLT4.COMPLINPUTXBAR10CLB6_5.1Reserved
24SD2FLT1.COMPHSD2FLT1.COMPH_OR_ COMPLReservedReserved
25SD2FLT1.COMPLReservedReservedCLB7_4.1
26SD2FLT2.COMPHSD2FLT2.COMPH_OR_ COMPLReservedReserved
27SD2FLT2.COMPLReservedERRORSTS.ERRORCLB7_5.1
28SD2FLT3.COMPHSD2FLT3.COMPH_OR_ COMPLXCLKOUTReserved
29SD2FLT3.COMPLReservedReservedCLB8_4.1
30SD2FLT4.COMPHSD2FLT4.COMPH_OR_ COMPLReservedReserved
31SD2FLT4.COMPLReservedReservedCLB8_5.1

Output X-BAR Mux Configuration Table - F28004x

Select MUX INPUT0123
OUTPUT# MUX select
0CMPSS1.CTRIPOUTHCMPSS1.CTRIPOUTH_OR_CTRIPOUTLADCAEVT1ECAP1OUT
1CMPSS1.CTRIPOUTLINPUTXBAR1CLB1_OUT4ADCCEVT1
2CMPSS2.CTRIPOUTHCMPSS2.CTRIPOUTH_OR_CTRIPOUTLADCAEVT2ECAP2OUT
3CMPSS2.CTRIPOUTLINPUTXBAR2CLB1_OUT5ADCCEVT2
4CMPSS3.CTRIPOUTHCMPSS3.CTRIPOUTH_OR_CTRIPOUTLADCAEVT3ECAP3OUT
5CMPSS3.CTRIPOUTLINPUTXBAR3CLB2_OUT4ADCCEVT3
6CMPSS4.CTRIPOUTHCMPSS4.CTRIPOUTH_OR_CTRIPOUTLADCAEVT4ECAP4OUT
7CMPSS4.CTRIPOUTLINPUTXBAR4CLB2_OUT5ADCCEVT4
8CMPSS5.CTRIPOUTHCMPSS5.CTRIPOUTH_OR_CTRIPOUTLADCBEVT1ECAP5OUT
9CMPSS5.CTRIPOUTLINPUTXBAR5CLB3_OUT4Reserved
10CMPSS6.CTRIPOUTHCMPSS6.CTRIPOUTH_OR_CTRIPOUTLADCBEVT2ECAP6OUT
11CMPSS6.CTRIPOUTLINPUTXBAR6CLB3_OUT5Reserved
12CMPSS7.CTRIPOUTHCMPSS7.CTRIPOUTH_OR_CTRIPOUTLADCBEVT3ECAP7OUT
13CMPSS7.CTRIPOUTLADCSOCAOCLB4_OUT4Reserved
14ReservedReservedADCBEVT4EXTSYNCOUT
15ReservedADCSOCBOCLB4_OUT5Reserved
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_COMPLReservedReserved
17SD1FLT1.COMPLReservedReservedCLAHALT
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_COMPLReservedReserved
19SD1FLT2.COMPLReservedReservedReserved
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_COMPLReservedReserved
21SD1FLT3.COMPLReservedReservedReserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_COMPLReservedReserved
23SD1FLT4.COMPLReservedReservedReserved

Output X-BAR Mux Configuration Table - F2807x and F2837x

Select MUX INPUT0123
OUTPUT# MUX select
0CMPSS1.CTRIPOUTHCMPSS1.CTRIPOUTH_OR_CTRIPOUTLADCAEVT1ECAP1OUT
1CMPSS1.CTRIPOUTLINPUTXBAR1CLB1_OUT4 ADCCEVT1
2CMPSS2.CTRIPOUTHCMPSS2.CTRIPOUTH_OR_CTRIPOUTLADCAEVT2ECAP2OUT
3CMPSS2.CTRIPOUTLINPUTXBAR2CLB1_OUT5 ADCCEVT2
4CMPSS3.CTRIPOUTHCMPSS3.CTRIPOUTH_OR_CTRIPOUTLADCAEVT3ECAP3OUT
5CMPSS3.CTRIPOUTLINPUTXBAR3 CLB2_OUT4ADCCEVT3
6CMPSS4.CTRIPOUTHCMPSS4.CTRIPOUTH_OR_CTRIPOUTLADCAEVT4ECAP4OUT
7CMPSS4.CTRIPOUTLINPUTXBAR4CLB2_OUT5 ADCCEVT4
8CMPSS5.CTRIPOUTHCMPSS5.CTRIPOUTH_OR_CTRIPOUTLADCBEVT1ECAP5OUT
9CMPSS5.CTRIPOUTLINPUTXBAR5CLB3_OUT4 ADCDEVT1
10CMPSS6.CTRIPOUTHCMPSS6.CTRIPOUTH_OR_CTRIPOUTLADCBEVT2ECAP6OUT
11CMPSS6.CTRIPOUTLINPUTXBAR6CLB3_OUT5 ADCDEVT2
12CMPSS7.CTRIPOUTHCMPSS7.CTRIPOUTH_OR_CTRIPOUTLADCBEVT3
13CMPSS7.CTRIPOUTLADCSOCAOCLB4_OUT4 ADCDEVT3
14CMPSS8.CTRIPOUTHCMPSS8.CTRIPOUTH_OR_CTRIPOUTLADCBEVT4EXTSYNCOUT
15CMPSS8.CTRIPOUTLADCSOCBO CLB4_OUT5ADCDEVT4
16SD1FLT1.COMPHSD1FLT1.COMPH_OR_COMPLReserved Reserved
17SD1FLT1.COMPLReserved Reserved Reserved
18SD1FLT2.COMPHSD1FLT2.COMPH_OR_COMPLReserved Reserved
19SD1FLT2.COMPLReserved Reserved Reserved
20SD1FLT3.COMPHSD1FLT3.COMPH_OR_COMPLReserved Reserved
21SD1FLT3.COMPLReserved Reserved Reserved
22SD1FLT4.COMPHSD1FLT4.COMPH_OR_COMPLReserved Reserved
23SD1FLT4.COMPLReserved Reserved Reserved
24SD2FLT1.COMPHSD2FLT1.COMPH_OR_COMPLReserved Reserved
25SD2FLT1.COMPLReserved Reserved Reserved
26SD2FLT2.COMPHSD2FLT2.COMPH_OR_COMPLReserved Reserved
27SD2FLT2.COMPLReserved Reserved Reserved
28SD2FLT3.COMPHSD2FLT3.COMPH_OR_COMPLReserved Reserved
29SD2FLT3.COMPLReserved Reserved Reserved
30SD2FLT4.COMPHSD2FLT4.COMPH_OR_COMPLReserved Reserved
31SD2FLT4.COMPLReserved Reserved Reserved

OUPUT# MUX (MUX 0 -> 31)

Indicates the input signal selected for each output# MUX. For example, XXXX1XXXXXXXXXXXXXXXXXXXXXXXXXX indicates that input signal 1 was selected for MUX 4. X indicates that the MUX is disabled and no signal from the MUX will be sent to the Output X-BAR output.

All the signals which are selected will be logically OR'd and sent to the output signal on the GPIO pin.

RESET OUPUT# MUX

Resets the signal selection for the MUX done so far.

Resets the OUTPUT# MUX (MUX 0->31) and Select MUX input inputs.

OUPUT# pin assignment

Select the GPIO pin to which the selected signals will be passed to. All signals from the MUXes which are enabled will be logically OR'd before being passed on to the respective OUTPUTx signal on the GPIO pin.

Enable OUTPUT# latch

Enable the output latch to latch the output signal on the GPIO pin. Latch signal has to be cleared manually.

Invert OUTPUT#

Select to invert the output signal to the GPIO pin.

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