This example shows how to model an HDL-optimized QPSK receiver and prototype it on the SDR hardware using the HDL Coder workflow advisor. In this example, the RF board under consideration is Analog Devices AD-FMCOMMS1 RevB/C, and the FPGA board is the Xilinx® ML605 development board.
Xilinx® ML605 development board
Xilinx® ISE Tools
AD-FMCOMMS1 RevB/C RF board
Communications System Toolbox™
Communications System Toolbox™ Support Package for Xilinx® FPGA-Based Radios
The commqpskrxhdl model walks through building a practical HDL-optimized digital receiver, which includes coarse frequency compensation, PLL-based fine frequency compensation, timing recovery, frame synchronization, phase ambiguity resolution, and QPSK demodulation. This example takes the next steps to generate HDL code from this HDL-optimized receiver and prototype it on the FPGA using the HDL Coder workflow advisor.
One possible source for the QPSK waveform generation is the companion sdrfqpsktx model. This source can be used to verify all three receivers: the behavioral sdrfqpskrx model, the HDL optimized sdrfQPSKRxFPGA model, and the FPGA prototype sdrfQPSKRxFPGAretarget model.
The structure of the QPSK receiver is shown in the figure below.
HDL-optimized part of the QPSK receiver is modeled under the subsystem HDLRx in this example, whose structure is shown in the diagram below.
Compared to the implementation of the HDLRx subsystem in the commqpskrxhdl model, everything stays the same except for the presence of the FPGA to Host subsystem after Data Decoding. To conform to the Xilinx® FPGA interface in the SDR platform, the output of the HDL-optimized QPSK receiver must be a 16-bit signed complex value. To meet this specific interface requirement, the subsystem FPGA to Host embeds the three Boolean signals (bit1, bit2, and dValid) into a 16-bit complex-valued integer.
Corresponding to the presence of the FPGA to Host subsystem in HDLRx, the Unpack FPGA Outputs subsystem extracts the three Boolean signals (bit1, bit2, and dValid) from the 16-bit signed complex values. The extracted Boolean signals are then fed to the dataframer subsystem.
You can follow the instructions below to generate HDL code for the HDLRx subsystem.
Open the HDL workflow advisor by right-clicking on the HDLRx subsystem and select HDL Code -> HDL Workflow Advisor.
In step 1.1 select Customization for an SDR Platform for Target workflow, and select Xilinx Virtex-6 ML605 development board for Target Platform.
Run steps 2.1 to 2.5 to make sure your model is compatible for HDL code generation.
Run steps 3.1 and 3.2 to generate the RTL code and testbench.
On step 4.1, select Analog Devices AD-FMCOMM1-EBZ RevB/C for RF board for target. The path of the HDL files provided by Analog Devices should auto-populate in the Folder with vendor HDL source code field.
If no error is found in FPGA project generation and syntax checking, the FPGA programming file generation process starts in an external command shell. You can monitor the external shell for the progress of implementation processes. A message indicating successful completion of programing file generation is printed out in the shell upon completion.
The HDL Workflow Advisor generates a programing file named HDLRx_sdrrx.bit in the folder hdl_prj/sdr_prj/fpgaproj. Use the following command to download the generated FPGA programming file:
sdrload('Device', 'Xilinx ML605', 'RFBoard', 'ADI FMCOMMS1 RevB/C', ... 'FPGAImage', './hdl_prj/sdr_prj/fpgaproj/HDLRx_sdrrx.bit');
The FPGA implementation of the QPSK receiver can be verified using a companion model sdrfQPSKRxFPGAretarget, whose receiver structure is shown in the following figure.
This model can be built from the original sdrfQPSKRxFPGA model by removing the Data Type Conversion block, the Unbuffer block, HDLRx, and the Buffer block. Note that this model no longer contains the HDLRx subsystem, as that is now implemented in FPGA.