This example shows how to use Ethernet based MATLAB as AXI Master to access the external memories connected to the FPGA. In the FPGA, there is a Xilinx DDR memory controller for accessing the DDR memories. This memory controller provides an AXI4 slave interface for read and write operations by other components in the FPGA. The Ethernet based MATLAB as AXI Master feature provides an AXI master component that can be used to access any AXI slave IPs in the FPGA. In this example, we demonstrate how to integrate this Ethernet based MATLAB as AXI Master into a Xilinx Vivado project, and read/write to the DDR memory using MATLAB.
Xilinx® Vivado® of compatible version
Xilinx Kintex-7 KC705 Evaluation Kit
HDL Verifier™ Support Package for Xilinx FPGA Boards
Ethernet cable and JTAG cable
Step 1: Set up FPGA board. Make sure that the Xilinx KC705 board is connected to the host computer via both Ethernet cable and JTAG cable. The JTAG cable is used for programming the device.
Step 2: Prepare example in MATLAB. Set up the Xilinx Vivado tool path. Use your own Xilinx Vivado installation path when executing the command. For example:
>> hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2018.2\bin\vivado.bat');
Create a folder outside the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that the folder is located at C:\MyTests.
Start MATLAB and set the current directory in MATLAB to the folder you just created. For example:
>> cd C:\MyTests
Copy the example files into current directory by executing this command in MATLAB.
Create a Vivado project for this example. This project contains the IP Integrator block diagram as well as constraint file that we created for this example.
>> system('vivado -mode batch -source createproject.tcl')
This command takes about one minute to finish. When it is done, a Vivado project named "ethernetaximaster.xpr" will exist in your current directory.
Step 3: Configure Vivado project with Vivado IP. To use the MATLAB as AXI Master IP inside Vivado IP Integrator, add the folder that contains the IP to the Vivado project's IP repository path setting. You can add the path to the project from MATLAB with this command:
>> setupAXIMasterForVivado ethernetaximaster.xpr
Open the generated Vivado project in GUI mode by double-clicking the project in a file browser, or execute this command in MATLAB:
>> system('vivado ethernetaximaster.xpr &')
Step 4: Add Ethernet MAC Hub and UDP MATLAB as AXI Master IPs to the FPGA design.
In the Vivado GUI, open the block diagram design file design_1.bd. You can find it in the source file sub-window.
The Ethernet based MATLAB as AXI Master IP has a default target IP Address of 192.168.0.2 and default UDP Port value of 50101. These values can be changed by double clicking on the ethernet_mac_hub IP in the block design.
Set the address of mig_7series_0 (memory controller) to 0x0000_0000 as shown:
Alternatively, you can complete the above setup steps by executing Tcl commands in Vivado.
Step 5: Generate FPGA programming file and program the FPGA. Click "Generate Bitstream" on the left of Vivado window to generate the FPGA programming file. Vivado might prompt you to save the project before moving forward. It takes about 5 to 10 minutes for Vivado to generate the bitstream file.
After generating the bitstream, make sure FPGA board is connected with Digilnet JTAG and Ethernet cable. Program the FPGA in MATLAB using the following command:
>> filProgramFPGA('Xilinx Vivado','ethernetaximaster.runs\impl_1\design_1.bit',1)
After programming the FPGA, you can read and write into the AXI slaves connected to the Ethernet based MATLAB as AXI Master IP. In this example, the data will be written to the DDR memory connected to the FPGA, and retrieved back into MATLAB.
First, create the AXI master object in MATLAB
>> h = aximaster('Xilinx', 'interface', 'UDP');
>> writememory(h, 0,100) >> readmemory(h, 0,1)