HDL Verifier™ Support Package for Xilinx® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier™ and supported Xilinx hardware. With FIL simulation, use MATLAB® or Simulink® to test designs in real hardware for any existing HDL code. The HDL code can either be manually written or generated from a model subsystem.
Install hardware support, update firmware, configure hardware connection
Verification with FPGA hardware
Capture signal data from live FPGA
Access AXI slave memory on FPGA board from MATLAB