Access on-board memory locations from MATLAB, using the MATLAB AXI Master IP in your FPGA
design, and the aximaster
object.
The object connects to the IP over the JTAG cable, and allows read and write
commands to slave memory locations from the MATLAB command line.
setupAXIMasterForVivado | Add AXI master IP path to Vivado project |
readmemory | Read data out of AXI4 memory-mapped slaves |
writememory | Write data to AXI4 memory-mapped slaves |
release | Release JTAG cable resource |
aximaster | Read and write memory locations on an FPGA board from MATLAB |
AXI Master Read | Read memory locations on FPGA board from Simulink |
AXI Master Write | Write memory locations on FPGA board from Simulink |
High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink®.
Integrate and configure Ethernet MATLAB as AXI Master using User Datagram Protocol (UDP).
PCI Express MATLAB as AXI Master
Integrate and configure of MATLAB as AXI Master IP over PCI Express.
Use Simulink to Access FPGA Locations
Access memory-mapped locations on an FPGA board from Simulink.