FPGA Data Reader

Capture data from live FPGA into Simulink model

• Library:

• Generated

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Description

The FPGA Data Reader block communicates with a generated IP core on an FPGA to return captured data into Simulink^®.

Before you run this block, you must generate the customized data capture components. Integrate the generated HDL IP core into your project and deploy it to the FPGA. The block communicates with the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and the host computer.

For a workflow overview, see Data Capture Workflow.

By default, the FPGA Data Capture Component Generator tool generates a data capture model that contains thisá block and a scope. If you have a DSP System Toolbox™ license, the captured data is streamed to the Logic Analyzer. Otherwise, the Scope block shows the captured data. You can add other blocks to the model for analysis, verification, and display.

Ports

The output ports of the FPGA Data Reader block correspond to the signals you requested to capture in FPGA Data Capture Component Generator. Set the data types for these ports in the Signal and Trigger Editor, opened from the block parameters.

Parameters

Sample time — Rate of output signals

double

The block returns one frame of data per time step, where the frame is the entire capture buffer for each signal. Each frame contains Sample depth values, as specified at generation time. The default sample time provides for unbuffering each frame into single samples, which results in a sample time of 1.

Trigger

Sample depth — Number of samples captured for each signal

integer

This parameter is read-only. It reflects the value you specified at generation time.

Number of capture windows — Number of data capture recurrences

1 (default) | integer power of two

Specify the number of recurrences to capture. This value must be a power of two, up to Sample depth. A window depth is defined as Sample depth / Number of capture windows. Consider the Number of capture windows when setting the Sample depth, to allow for sufficient buffering.

Number of trigger stages — Number of trigger stages for providing trigger conditions

M (default) | integer from 1 to M

Specify the number of trigger stages. This value must be an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool. When you specify the Max trigger stages parameter, consider the maximum number of trigger stages in which you plan to configure the trigger conditions to capture data.

Trigger position — Position of trigger detection cycle within capture buffer

0 (default) | integer up to window depth -1

By default, the clock cycle when the trigger is detected is the first sample of the capture buffer. You can change the relative position of the trigger detection cycle within the capture buffer. A nondefault trigger position means that some samples are captured before the trigger occurs. You can set this parameter to any number between 0 and window depth-1, inclusive. When the trigger position is equal to the window depth-1, the last sample corresponds to the cycle when the trigger occurs. If Number of capture windows is greater than one, the same trigger position applies to all windows. See Triggers.

Trigger combination operator — Logical operator to combine comparisons of individual signals into overall trigger condition

AND (default) | OR

This parameter is indicated by the logic gate icon. Press the Change operator button to toggle between AND and OR.

The trigger condition can be composed of value comparisons of one or more signals. Combine these value comparisons with only one type of logical operator. Suppose three signals, A, B, and C, make up the trigger condition. The options are:

A == 10 AND B == 'Falling edge' AND C == 0

or

A == 10 OR B == 'Falling edge' OR C == 0

You cannot mix and match the combination operators. See Triggers.

Signal — Trigger component signal name

character vector

This parameter is read only. The signal names you specified at generation time are listed in the drop-down menu at the bottom. Press the + button to add a signal to the trigger condition.

Operator — Operator to compare signals within trigger condition

== | != | < | > | <= | >=

To compare signals, select one of these operators: ==, !=, <, >, <=, or >=. To compare signals containing X or x (don't-care value), specify either == or != operator.

Value — Value to compare this signal to as part of overall trigger condition

decimal | binary | hexadecimal | Low | High | Rising edge | Falling edge | Both edges

The trigger condition can be composed of value comparisons of one or more signals. This parameter specifies the value to match for each signal.

For a multi-bit signal, specify a decimal, binary, or a hexadecimal value within the range of the data type associated with the signal. While providing hexadecimal or binary values, you can provide values with a combination of X or x (don't care value) to enable bit masking. That means, while comparing the values, the trigger condition discards the place values with X or x and provides the output.

To separate a group of bits for better readability, you can use _ between bits. For example, you can represent a 32-bit binary value as 0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXX and a 32-bit hexadecimal value as 0xAB_CDEXFX.

For boolean signals, select a level or edge condition. See Triggers.

Trigger time out — Maximum number of FDC IP core clock cycles within which trigger condition must occur in a trigger stage

1 (default) | integer from 1 to 1,048,576

Within this many FPGA Data Capture (FDC) IP core clock cycles, the trigger condition must occur in a trigger stage in which you are enabling this parameter. You can specify any integer value from 1 to 1,048,576 according to your requirements.

Dependencies

Select this parameter to enable trigger time out in a trigger stage. A trigger time out is not allowed in Trigger Stage 1.

Time out — Number of seconds to wait before aborting data capture, if the trigger condition is not met

10 (default) | positive integer

If a trigger condition is enabled, but the HDL IP core does not detect the condition, the data capture request times out after this many seconds. No data is returned to Simulink.

Data Types

Signal — Name of output port

character vector

This parameter is read only. It reflects the value you specified at generation time.

Bit Width — Number of bits in signal

positive integer

This parameter is read only. It reflects the value you specified at generation time.

Data Type — Data type for captured data

built-in type | numerictype

The Data Type menu provides data type suggestions that match the bit width of the captured signal. This size is the width you specified for the port on the generated IP. You can type in this field to specify a custom data type. If the signal is 8, 16, or 32 bits, the default is uint. If the signal has one bit, the default is boolean. If the signal is a different width, the default is numerictype(0,bitWidth,0).

If your development board has multiple FPGAs or multiple JTAG connections, the data capture software cannot detect the location of your FPGA in the JTAG chain. Specify these advanced parameters to locate the FPGA that contains the data capture IP core.

Advanced Board Setup

JTAG Cable Name — Name of JTAG cable used for data capture

auto (default) | character vector

Name of the JTAG cable used for data capture, specified as a character vector. Use this argument when the board is connected to two JTAG cables of the same type.

JTAG Cable Type — Type of JTAG cable used for communication with FPGA board

'auto' (default) | 'FTDI'

Specify this property if more than one JTAG cable is connected to the host computer. When not specified, the FPGA Data Reader block will auto-detect the JTAG cable type, in the following order:

• The FPGA Data Reader block first searches for a Digilent^® cable.

• If it does not find a Digilent JTAG cable, it searches for an FTDI cable.

• If it finds two cables of the same type, the object returns an error. Specify JTAGCableName to resolve it.

• If it finds two cables of different types, it will prioritize the Digilent cable. To use an FTDI cable, set this argument to 'FTDI'.

JTAG chain position — Position of FPGA in JTAG scan chain

0 (default) | positive integer

Position of the FPGA in the JTAG scan chain, specified as a positive integer.

Instruction registers before FPGA — Instruction register lengths before FPGA

0 (default) | non-negative integer

Number of instruction register lengths before the FPGA, specified as a non-negative integer.

Instruction registers after FPGA — Instruction register lengths after FPGA

0 (default) | non-negative integer

Number of instruction register lengths after the FPGA, specified as a non-negative integer.

Tck frequency — JTAG clock frequency

15 (default) | integer

Specify the JTAG clock frequency, in MHz. For Xilinx^® FPGAs, the JTAG clock frequency is 33 or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.