Capture data from live FPGA into Simulink model
Generated
The FPGA Data Reader block communicates with a generated IP core on an FPGA to return captured data into Simulink®.
Before you run this block, you must generate the customized data capture components. Integrate the generated HDL IP core into your project and deploy it to the FPGA. The block communicates with the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and the host computer.
For a workflow overview, see Data Capture Workflow.
By default, the FPGA Data Capture Component Generator tool generates a data capture model that contains thisá block and a scope. If you have a DSP System Toolbox™ license, the captured data is streamed to the Logic Analyzer. Otherwise, the Scope block shows the captured data. You can add other blocks to the model for analysis, verification, and display.
The output ports of the FPGA Data Reader block correspond to the signals you requested to capture in FPGA Data Capture Component Generator. Set the data types for these ports in the Signal and Trigger Editor, opened from the block parameters.