To read and write memory-mapped locations on your FPGA board using Simulink®, you must first integrate a MATLAB® AXI master IP into your FPGA design. For more information, see Integrate MATLAB AXI Master IP in FPGA Design.
Configure the AXI Master Write block. Set the write Address, and the Burst type. On the Interface tab, select the interface type, and select Configure global parameters to configure the global interface parameters for the AXI master interface.
Next, configure the AXI Master Read block. Set the read Address, and the Burst type as well as the Output data type and Output vector size parameters. On the Interface tab, select the interface type used for AXI master communication.
On the toolstrip, click run to simulate the model. On every Simulink step, the write block writes to the FPGA, and the read block reads from it. You can now view the results using Logic Analyzer, or by directing the data to a file.
In this example, the AXI Master Write block writes
100 to address
0, and the AXI Master
Read block reads from the same address. The following image shows the input
data and the output data displayed in Logic Analyzer.