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AD9361 Rx

Connect hardware logic to AD9361-based Zynq receiver

  • Library:
  • SoC Blockset Support Package for Xilinx Devices / SDR / AD9361

  • AD9361 Rx block

Description

The AD9361 Rx block connects your hardware logic to the AD9361 receiver hardware. In simulation, this block returns data from a file or input port. This block does not connect to the radio hardware from simulation.

Ports

Input

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Receiver data to pass through the block in simulation.

Dependencies

To enable this port, set the Simulation output parameter to From input port.

Data Types: uint32

Output

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Receiver data, returned as a scalar. The Simulation output parameter defines the source of this data.

Data Types: uint32

Parameters

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Simulation behavior, specified as one of these values:

  • Zeros –– Return zero-valued data.

  • From recorded file –– Return data from a file, using the Dataset name and Source name parameters.

  • From input port –– Pass through data from the input port.

Name of recorded file, specified as a file path on the host PC or browse and select the file on the host PC. This block supports only TGZ files created using the SoC Blockset™ data recording API. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.

Name of a dataset available within the recorded dataset file, specified as a character vector. The dataset must exist in the file specified in the Dataset name parameter. You can either type the name in the Source name box or click Select to view a list of sources available in the recorded data file and examine their properties. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.

Sample time of the block, specified as a positive scalar.

Data Types: double

Extended Capabilities

Version History

Introduced in R2019a

See Also