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ADC To Vector

Convert concatenated 16-bit ADC input samples to vector outputs

  • Library:
  • SoC Blockset Support Package for Xilinx Devices / SDR / RFDataConverter

  • ADC To Vector block icon

Description

The ADC To Vector block converts the concatenated 16-bit analog-to-digital converter (ADC) input samples to vector outputs.

The block accepts 16-bit samples packed into N x 16 bits through the adcData input port and outputs a vector of N samples through the vectorData output port. N is the number of samples per clock cycle.

Ports

Input

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ADC data samples, specified as a scalar. The size of this input must be N x 16 bits, where N is the number of samples per clock cycle set by the Samples per clock parameter.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

Output

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ADC data samples, returned as a vector. The block returns the data as an N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock parameter.

For example, consider the case where N = 2 and the input to the adcData port is of size 32 bits. In this case, the block returns vector [S0, S1], where S0 is a 16-bit value sliced from 0 to 15 bits of input data from the adcData port, and S1 is a 16-bit value sliced from 16 to 31 bits of input data from the adcData port.

Data Types: int16 | uint16

Parameters

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Specify the number of samples per clock cycle as an integer from 1 to 16. This parameter sets the required bit width of the input samples and sets the output vector size.

Specify the output data type as a signed or unsigned fixed point or an integer data type. For more information on how to specify output data type, see Specify Data Types Using Data Type Assistant.

Extended Capabilities

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Version History

Introduced in R2020b