RF Data Converter

Provide RF data path interface to hardware logic

  • Library:
  • SoC Blockset Support Package for Xilinx Devices / SDR / RFDataConverter

  • RF Data Converter

Description

The RF Data Converter block provides an RF data path interface to the hardware logic.

The block accepts 16-bit samples packed into N x 16 bits through dacxData ports and outputs a vector of N samples through dacx ports. The block accepts a vector of N samples through adcx ports and outputs 16-bit samples packed into N x 16 bits through adcxData ports based on the N value. N is the number of samples per clock cycle, and the possible values of x range from 1 to 8. The block supports a maximum of eight analog-to-digital converter (ADC) and eight digital-to-analog converter (DAC) data paths connecting to the hardware logic.

In generation, the SoC Builder tool maps the block parameters to the RF Data Converter IP on the hardware.

Ports

Input

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ADC input data, specified as a column vector.

x indicates the number of adc ports and ranges from 1 to 8. The RF interface parameter sets the number of adc ports. For example, if RF interface is set to ADC & DAC 2x2 RF Interface, the block has ports adc1 and adc2, that is, one input port per ADC channel interface.

Valid values for this port are based on the Digital interface parameter value.

  • If you set the Digital interface parameter to Real, specify this value as an N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

    Use this option to specify real-valued data. For example, consider N equal to 2 and data containing two real values D0 and D1. In this case, specify this port value as a vector of the form [D0 D1].

  • If you set the Digital interface parameter to I/Q, specify this value as a 2N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

    Use this option to specify complex-valued data. For example, consider N equal to 2 and data containing two complex values with real parts I0 and I1 and imaginary parts Q0 and Q1, respectively. In this case, specify this port value as a vector of the form [I0 Q0 I1 Q1].

Data Types: int16 | uint16

DAC input data, specified as a scalar.

x indicates the number of dacxData ports and ranges from 1 to 8. The RF interface parameter sets the number of dacxData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to Real.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

Real part of DAC input, specified as a scalar.

x indicates the number of dacxIData ports and ranges from 1 to 8. The RF interface parameter sets the number of dacxIData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

Imaginary part of DAC input, specified as a scalar.

x indicates the number of dacxQData ports and ranges from 1 to 8. The RF interface parameter sets the number of dacxQData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

Indication of valid DAC input data, specified as a scalar.

A value of 1 indicates when the data on the dacxData port is valid or when the data on the dacxIData and dacxQData ports is valid.

x indicates the number of dacxValid ports and ranges from 1 to 8. The RF interface parameter sets the number of dacxValid ports.

Data Types: Boolean

Output

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DAC output data, returned as a column vector.

  • If you set the Digital interface parameter to Real, the block returns outputs as a N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

    For example, consider N equal to 2 and input to the dac1Data port is of size 32 bits. In this case, this port returns a vector [S0 S1], where S0 is a16-bit value sliced from 0 to 15 bits of input data on the dac1Data port and S1 is a 16-bit value sliced from 16 to 31 bits of input data on the dac1Data port.

  • If you set the Digital interface parameter to I/Q, the block returns outputs as a 2N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

    For example, consider N equal to 2 and inputs to dac1IData and dac1QData ports are of size 32 bits. In this case, this port returns a vector [I0 Q0 I1 Q1], where I0 is a16-bit value sliced from 0 to 15 bits of input data on the dac1IData port and I1 is a 16-bit value sliced from 16 to 31 bits of input data on the dac1IData port and Q0 is a16-bit value sliced from 0 to 15 bits of input data on the dac1QData port and Q1 is a 16-bit value sliced from 16 to 31 bits of input data on the dac1QData port.

x indicates the number of dacx ports and ranges from 1 to 8. The RF interface parameter sets the number of dacx ports.

Data Types: int16

ADC output data, returned as a scalar.

x indicates the number of adcxData ports and ranges from 1 to 8. The RF interface parameter sets the number of adcxData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to Real.

Data Types: uint16 | uint32 | uint64 | fixed point

Real part of ADC output, returned as a scalar.

x indicates the number of adcxIData ports and ranges from 1 to 8. The RF interface parameter sets the number of adcxIData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: uint16 | uint32 | uint64 | fixed point

Imaginary part of ADC output, returned as a scalar.

x indicates the number of adcxQdata ports and ranges from 1 to 8. The RF interface parameter sets the number of adcxQdata ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: uint16 | uint32 | uint64 | fixed point

Indication of valid ADC output data, returned as a scalar.

A value of 1 indicates that the data on the adcxData port is valid or that the data on the adcxIData and adcxQData ports is valid.

x indicates the number of adcxValid ports and ranges from 1 to 8. The RF interface sets the number of adcxValid ports.

Data Types: Boolean

Parameters

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Specify the RF channel interface type.

To select a predefined set of ADC and DAC combinations, set this parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, or ADC & DAC 8x8 RF Interface. To select the required number of DAC or ADC combinations, set this parameter to Customize.

Example: ADC & DAC 2x2 RF Interface specifies two ADC and two DAC RF channel interfaces.

Specify the digital interface type.

  • Real – Supports real data

  • I/Q – Supports complex data by using real and imaginary ports

Select this parameter to enable multitile synchronization (MTS).

In generation, the Xilinx® RF Data Converter tool provides synchronization clocks and ADC and DAC clocks to the RF Data Converter hardware IP. In MTS mode, these synchronization clocks depend on the ADC and DAC sampling rates. Because, the Xilinx RF Data Converter tool provides a set of fixed default synchronization clocks in MTS mode and supports only these sample rates: 737.28, 1474.56, 1966.08, 2457.6, 2949.12, 3072, 3932.16, 4669.44, 4915.2, 5898.24, and 6144.

When you enable this parameter, the block supports only a single sample rate: 1966.08.

For more information on MTS mode, see the Xilinx Documentation PDF.

DAC

The DAC tab contains two panes: Tile1 and Tile2. Each pane contains four DACs. The Tile1 pane accommodates DAC1, DAC2, DAC3, and DAC4. The Tile2 pane accommodates DAC5, DAC6, DAC7, and DAC8. The tiles and DACs shown on the block mask indicate the corresponding tiles and DACs on the selected hardware board.

The selection of tiles and the respective DACs is predefined when you set the RF interface parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, or ADC & DAC 8x8 RF Interface. You cannot modify the tile and DAC selection when you select these predefined options. To modify the tile and DAC selections, set the RF interface parameter to Customize.

Select this parameter to apply the same parameter values to all of the selected DACs.

Clear this parameter to specify different parameter values for each of the selected DACs.

Dependencies

To enable this parameter, set the RF interface parameter to Customize.

Specify the sample rate in mega samples per second.

When you enable the Multi tile sync parameter, the block supports only a single sample rate: 1966.08.

Specify the interpolation factor.

Specify the number of samples per clock cycle.

The block calculates the stream data width as 16 x Samples per clock cycle.

The block calculates the stream clock frequency as Sample rate (MSPS) / Interpolation mode (xN) x Samples per clock cycle.

Specify the mixer type.

To use Bypassed, set the Digital interface parameter to Real.

To select either Coarse or Fine, set the Digital interface parameter to I/Q.

This parameter is read-only.

To use Real->Real, set the Digital interface parameter to Real.

To use I/Q->Real, set the Digital interface parameter to I/Q.

Specify the mixer frequency.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Coarse.

Specify the numerically controlled oscillator (NCO) frequency values as an m-element row vector, where m is the number of DACs.

When you set the RF interface parameter to Customize and clear the Match parameters of all DACs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and the Mixer type parameter to Fine.

Specify the NCO phase as an m-element row vector, where m is the number of DACs.

When you set the RF interface parameter to Customize and clear the Match parameters of all DACs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and the Mixer type parameter to Fine.

Select this parameter to convert the analog sinc output response from the DAC to a flat-output response.

ADC

The ADC tab contains four panes: Tile1, Tile2, Tile3, and Tile4. Each pane contains two ADCs. The Tile1 pane accommodates ADC1 and ADC2. The Tile2 pane accommodates ADC3 and ADC4. The Tile3 pane accommodates ADC5 and ADC6. The Tile4 pane accommodates ADC7 and ADC8. The tiles and ADCs shown on the block mask indicate the corresponding tiles and ADCs on the selected hardware board.

The selection of tiles and the respective ADCs is predefined when you set the RF interface parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, or ADC & DAC 8x8 RF Interface. You cannot modify the tile and ADC selection when you select these predefined options. To modify the tile and ADC selections, set the RF interface parameter to Customize.

Select this parameter to apply the same parameter values to all of the selected ADCs.

Clear this parameter to specify different parameter values for each of the selected ADCs.

Dependencies

To enable this parameter, set the RF interface parameter to Customize.

Specify the sample rate in mega samples per second.

When you enable the Multi tile sync parameter, the block supports only a single sample rate: 1966.08.

Specify the decimation factor.

Specify the number of samples per clock cycle.

The block calculates the stream data width as: 16 x Samples per clock cycle.

The block calculates the stream clock frequency as: Sample rate (MSPS) / Decimation mode (xN) x Samples per clock cycle.

Specify the mixer type.

To use Bypassed, set the Digital interface parameter to Real.

To select either Coarse or Fine, set the Digital interface parameter to I/Q.

This parameter is read-only.

To use Real->Real, set the Digital interface parameter to Real.

To use Real->I/Q, set the Digital interface parameter to I/Q.

Specify the mixer frequency.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Coarse.

Specify the numerically controlled oscillator (NCO) frequency values as an m-element row vector, where m is the number of ADCs.

When you set the RF interface parameter to Customize and clear the Match parameters of all ADCs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Fine.

Specify the NCO phase as an m-element row vector, where m is the number of ADCs.

When you set the RF interface parameter to Customize and clear the Match parameters of all ADCs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Fine.

Model Examples

More About

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Compatibility Considerations

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Behavior changed in R2020b

Extended Capabilities

See Also

Introduced in R2020a