This example shows how to simulate and deploy a 5G NR Cell Search algorithm in Simulink® using an SoC Blockset® implementation targeted on the Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can recover and demodulate a primary synchronization signal (PSS) and secondary synchronization signal (SSS) from the 5G NR waveforms and simulate the Cell Search control algorithm sequence running on a processor while interacting with the Cell Search hardware algorithm. In simulation, you can fine tune and verify the controller in the processor and hardware algorithm in the FPGA at a system level before implementing them on the hardware.
Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit + XM500 Balun card + Band Pass Filter:3000-4300 MHz
In this example, the design task is to build a wireless communication system for a 5G application and implement the system on a Xilinx RFSoC device. The cell search algorithm in this example is the NR cell search algorithm from the NR HDL Cell Search and MIB Recovery MATLAB Reference (Wireless HDL Toolbox) example. This figure shows the conceptual overview of the cell search algorithm.
The SS Block Detector performs all the high-speed signal processing tasks, making the SS Block Detector well suited for FPGA implementation on the programmable logic (PL). To implement the SS Block Detector in the PL, this example uses the Simulink® hardware model from the NR HDL Cell Search (Wireless HDL Toolbox) example as a model reference.
The Search Controller coordinates the search and operates at a low rate, making the Search Controller well suited for software implementation on the integrated ARM® processing system (PS). For the software implementation, this example uses the Search Controller algorithm described in the NR HDL Cell Search and MIB Recovery MATLAB Reference (Wireless HDL Toolbox) example.
5G RF Carrier frequency: 3560 MHz
Cell Search receive algorithm sample rate: 61.44 MSPS
Create an SoC model soc_5GNRCellSearch_top as the top model and set the hardware board to Xilinx Zynq Ultrascale+ RFSoC ZCU111 evaluation kit. This model includes FPGA model soc_5GNRCellSearch_fpga and processor model soc_5GNRCellSearch_proc, which are instantiated as model references. The top model also includes Memory Channel and Memory Controller blocks that share the external memory between the FPGA and the processor.
Create an SoC model soc_5GNRCellSearch_hwtop as the top model for the simulation of a hardware algorithm with a static configuration. This model includes the FPGA model soc_5GNRCellSearch_fpga.
RF Data Converter Configuration
An RFSoC device has its RF data converter connected to the programmable logic. To configure the ADC and DAC settings, use the RF Data Converter (RFDC) block. The block provides an interface to the Xilinx RF Data Converter IP in Simulink for modeling a wireless system destined for implementation on Xilinx RFSoC device.
To meet the system requirements of a 3560 MHz 5G RF carrier frequency and 61.44 MSPS baseband sample rate, configure the RF Data Converter block according to these values. NCO frequency for the DAC and ADC mixers is set to 3.560 GHz and the ADC and DAC sample rate is set to 3932.16 MSPS, you must choose the values of Interpolation mode (xN), Decimation mode (xN), and Samples per clock cycle parameters such that the effective clock cycle (sample rate) for the wireless algorithm FPGA is the desirable value and for this example: 61.44 MSPS. This is calculated and displayed on the block mask as the Stream clock frequency (MHz) parameter after you click Apply. Set the Decimation mode (xN) to 8, then effective sample rate after decimation is 491.52 MSPS. To get the clock cycle (baseband sample rate) to 61.44 MSPS, set the Samples per clock cycle to 8. Similarly set Interpolation mode (xN) to 8 and Samples per clock cycle is 8 in DAC tab. This will imply the Stream clock frequency to be 3932.16/(8*8) = 61.44 MHz.
Hardware Logic Design
FPGA model soc_5GNRCellSearch_fpga contains three subsystems: Transmit Repeat, Vector interpolation (which is connected to the DAC portion of the RFDC block), and the 5G Cell Search Receive (which is connected to the ADC portion of the RFDC block).
In the 5G Cell Search Receive subsystem, the Vector Decimator block receives the packed eight samples as 128 bits. The Vector Decimator block decimates input vector samples by eight and sends to the 5G Cell Search Receive subsystem. The sample rate after the vector decimator is 61.44 MSPS, as expected by the 5G cell search algorithm for its processing. For the complete design of the 5G cell search algorithm, see the NR HDL Cell Search (Wireless HDL Toolbox) example as a model reference. The cell search algorithm sends PSS reports as a stream data to the search controller running on the processor through a memory channel.
To provide a test 5G NR waveform, build a transmitter that reads the data samples from Block RAM and sends it to the DAC portion of the RFDC. The data samples are written from the processor using the data path from processing system using the DDR memory. The Vector Interpolation block interpolates the input samples from the transmit repeat sub system by eight (491.52 MSPS) and sends as vector of eight samples at a time. All eight samples are packed together as 128 bits AXI-Stream data and sent to the DAC. This figure shows the sample rate flow in the FPGA transmit and receive path.
In the receive path, the Vector Decimator block receives the packed eight samples with a sample rate of 491.52 MSPS from the RF Data Converter block. The Vector Decimator block decimates input vector samples by eight and sends to the Cell Search Receiver. The sample rate after the vector decimator is 61.44 MSPS as expected by the Cell Search Receiver for its processing. The Cell Search Receiver sends the processed data to processor with sample time of 61.44 MHz. In the transmit path, processor writes 5G test waveform samples to FPGA Block RAM with sample rate of 61.44 MSPS. The Block RAM sends the samples continuously to the RF Data Converter through Vector Interpolation block by using transmit repeat logic. The Vector Interpolation block interpolates the input samples by eight (491.52 MSPS) and sends to the RF Data Converter block as a vector of eight samples.
Processor Logic Design
The processor logic contains a write task, read task, and periodic task. The periodic task is a timer-driven task with a periodic time of 1e-3 that is defined in the task manager. The periodic task drives the Cell Search Controller block. The Cell Search Controller block configures and controls the hardware algorithm through the AXI4-Lite registers based on the status received through the AXI4-Lite read registers and stream read interface. The controller provides the cell search reports to MATLAB host using UDP blocks after valid PSS and SSS are detected. The UDP Write PSSReport and UDP Write SSSReport subsystems relay the PSS report and SSS report, respectively, to the host over the UDP protocol.
The read task is an event-based task driven by the arrival of data from the FPGA through DDR memory. This data comprises the information required for generating the PSS and SSS reports such as CellID and signal-to-noise ratio (SNR). The processor algorithm task is denoted as dataTask in the Task Manager block and is specified as an event-driven task. The write task is an event-based task used for transferring test waveform from the processor to the FPGA. All the above tasks are modeled under Processor Algorithm Wrapper subsystem in processor model soc_5GNRCellSearch_proc and connected to the Task Manager block at the top level.
The processor sends PSS and SSS reports to the host over Ethernet using UDP Write blocks. The IP address of the UDP Write block in the processor model should be configured to the IP address of the host.
This interface model running on the host shows how to receive the data and reports to the MATLAB workspace. You can use the rocker switch to select between automatically stopping the model after an SSS is demodulated or indefinitely streaming the reports.
To confirm basic operation, you can run the hardware model using a generated 5G NR waveform. You can generate a waveform using the
generate5GBurstWaveform function. The model calls this function in the initialization callback and assigns the waveform to the workspace variable
burstWaveform. Because the 5G Cell Search Receive subsystem contains a large number of HDL-optimized blocks requiring simulation using sample-based signals running at high sample rates, full simulation can take a while. You can find a simulation of the SS Block Detector model reference functionality in the NR HDL Cell Search (Wireless HDL Toolbox) example.
You can use this hardware model to quickly simulate and verify the hardware functionality using the test harness. To model the transmit path in the hardware model to loopback with the receiver through the RF Data Converter block, the test harness uses the generated 5G NR waveform as an input. You can switch between simulating the model in search or demodulation modes by double-clicking the manual switch block. In search mode, the model reaches hardware state 3, which means a PSS is detected. The search generates a PSS report for each PSS detection. These reports are zero-padded to 241 entries and logged to the MATLAB workspace. In demodulation mode, the model reaches state 8, indicating that the SSB is demodulated and its SSS is detected. The model also returns the zero-padded 241-entry PSS report. You can simulate this hardware model for only static configuration.
If you want to see the complete hardware and software simulation of the cell search algorithm and the controller dynamic configuration for multiple frequency searches, run the 5G NR cell search top model. To see the detected PSS and its demodulation, this model must run for at least 180 milli seconds. See the Simulation Data Inspector to monitor the hardware and software status signals. The Simulation Daata Inspector plots the progress of the cell search algorithm including the start and restart pulses, the frequency offset in Hz, and the hardware (SS block detector) state.
PSS search operation completed, PSS found, demodulation done, and found SSS states are clearly visible from the hardware state signal in the above Simulation Data Inspector plots.
To see the PSS and SSS reports in the host, run the host model, and then run the 5G NR cell search top model. When the host interface model runs successfully, the model displays the received signal-to-noise ratio (SNR) of the PSS and SSS in dB along with the decoded cell ID. For further processing, the model also exports two timeseries variables to the MATLAB workspace:
Connect the SMA connector and Band Pass Filter: 3000-4300 MHz on the XM500 Balun card to complete the loopback between the DAC and ADC, according to these connections.
DAC229_T1_CH0(J7) to ADC225_T1_CH0(J2).
To implement the model on a supported SoC board, use the SoC Builder tool. Ensure that the Hardware Board is set to
Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit in the System on Chip tab of the Simulink toolstrip.
To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.
Select 'Build Model' on the Setup screen. Click 'Next'.
Click 'View/Edit Memory Map' on the Review Memory Map screen to view the memory map. Click 'Next'.
Specify the project folder on the Select Project Folder screen. Click 'Next'.
Select 'Build External mode' on the Select Build Action screen. Click 'Next'.
Click 'Validate' on the Validate Model screen to check the compatibility of the model for implementation. Click 'Next'.
Click 'Build' on the Build Model screen to begin building the model. An external shell opens when FPGA synthesis begins. Click 'Next'.
Click 'Test Connection' on Connect Hardware screen to test the connectivity of the host computer with the SoC board. Click 'Next' to go to the Run Application screen.
The FPGA synthesis may take more than 30 minutes to complete. To save time, you can use the provided pregenerated bitstream by following these steps.
Close the external shell to terminate the FPGA synthesis.
Copy the pregenerated bitstream to your project folder by entering this command at the MATLAB command prompt.
Click 'Load and Run' button to load the pregenerated bitstream and run the model on the SoC board.
After the bit file is loaded, open the generated software model.
Run the model in external mode by clicking Monitor & Tune. You can control the configuration from the Simulink model.
You can use the Simulation Data Inspector from the software model to monitor the hardware and software. The Simulation Data Inspector plots the progress of the cell search algorithm including the start and restart pulses, the frequency offset in Hz, and the hardware (SS block detector) state.
Generate PSS and SSS Reports from Hardware
Run the host model to see the PSS and SSS reports. When the host interface model runs successfully, the model displays the received SNR of the PSS and SSS in dB along with the decoded cell ID. For further processing, the model also exports two timeseries variables to the MATLAB workspace:
This example shows how to integrate the 5G NR cell search algorithm on a Xilinx ZCU111 evaluation board using SoC Blockset and then how to verify the design in simulation and on hardware. The implementation recovers and demodulates PSS and SSS symbols from 5G NR waveforms.