OFDM Transmit and Receive Using Analog Devices AD9361/AD9364
This example shows how to deploy an orthogonal frequency division multiplexing (OFDM) transmit and receive algorithm on the Analog Devices AD9361/AD9364 radio platform.
The example combines the hardware-optimized Simulink® models in the HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples to design a deployable Simulink model. The example uses the hardware-software (HW/SW) co-design work flow to deploy the Simulink model onto the radio hardware platforms.
For a list of supported radio hardware platforms, see Hardware Support. Due to limited hardware resources, this example does not support Avnet ZedBoard and FMCOMMS2/3/4.
This figure shows the conceptual overview of the example.
The OFDM Transmitter and OFDM Receiver perform all the high-speed signal processing tasks, making the OFDM-based transmit and receive algorithm well suited for FPGA implementation on the programmable logic (PL) of the radio platform. The example is equipped with an internal channel to apply carrier frequency offset (CFO) and an HDL AWGN channel from the HDL Implementation of AWGN Generator (Wireless HDL Toolbox) example. Control signals insertCFO and snrdB are provided to tune the channel.
To work with the HW/SW co-design workflow, you must install and configure additional support packages and third-party tools. For more information, see Installation for Hardware-Software Co-Design.
Hardware Generation Model
This figure shows the high level overview of the OFDM-based transmit and receive algorithm model. Using this model, you can generate the HDL code for the PL and generate a template software interface model for the PS using the HDL Workflow Advisor. Using the template software interface model, you can generate an application that runs on the PS.
To open the hardware generation model, click open model.
OFDM HDL subsystem contains the functionality to be implemented on the PL. This subsystem contains an OFDM Transmitter and an OFDM Receiver connected back-to-back. This model is equivalnent to the Simulink model in the HDL OFDM MATLAB References (Wireless HDL Toolbox) example. Also, this model provides additional functionality to integrate it with the Zynq® hardware architecture.
This subsystem generates the status signals information from the OFDM Receiver and displays the number of frames synchronized, estimated CFO, decoded header information, number of header and data CRC pass and failures, number of bits received, and number of bit errors. ARM processor pulls the status signals information from the FPGA and displays the information on the host.
OFDM Tx Channel OFDM Rx| subsystem includes the following subsystems:
OFDM Tx— Implemented from the HDL OFDM Transmitter example.
OFDM Rx— Implemented from the HDL OFDM Receiver example.
Channel Control— Contains
White Gaussian Noise Generatorand
Apply CFOsubsystems. The
White Gaussian Noise Generatorsubsystem contains an AWGN Generator implemented from the HDL Implementation of AWGN Generator example. The
Apply CFOsubsystem performs the CFO insertion using the NCO (DSP HDL Toolbox) block.
Select Payload datasubsystem has an LUT, which stores the data bits used for transmitter waveform generation.
Simulate Hardware Generation Model
To simulate the model, run the hardware generation model. The model callback initialization loads the
dataBits to the workspace. To access the callback initialization, select MODELING > Model Settings > Model Properties > Callbacks > InitFcn.
The simulation may take some time because the model has several HDL-optimized blocks that must be simulated using sample-based signals. Double-click Control Scope to view the Tx Filtered Spectrum, Header Constellation, and Data Constellation displays before the simulation has begun.
You can control the channel using the input ports insertCFO and snrdB. When enableInternalLoopback is set to
false, the OFDM signals are transmitted and received externally through the Tx and Rx antennas, where the channel impairments are added over-the-air in real time.
After completing the simulation, generate the HDL IP core, integrate it with the SDR reference design, and generate software template model for the ARM processor using HDL Workflow Advisor.
Generate IP Core
To generate the HDL IP core, right-click the
OFDM HDL subsystem and select HDL Code > HDL Workflow Advisor.
Expand 1. Set Target and click 1.1. Set Target Device and Synthesis Tool. In the right pane, set Target workflow to
IP Core Generationand Target platform to
ZC706 and FMCOMMS2/3/4.
Click 1.2. Set Target Reference Design. In the right pane, set Reference design to
Receive and Transmit path. For this example, use the default settings in the Reference design parameters pane.
Click 1.3. Set Target Interface. In the right pane, under the Target platform interface table pane map the DUT signals to the interface signals available in the reference design. Because this example uses a single channel, configure the channel 1 connections and AXI register interfaces as shown in these figures.
Click 1.4. Set Target Frequency. In the right pane, set Target Frequency (MHz) to 61.44. For this example, use the default settings in the Set Target Frequency pane.
Click 2. Prepare Model for HDL Code Generation. In the right pane, click Run All. The app prepares the model for HDL code generation by performing design checks.
Click 3. HDL Code Generation. In the right pane, click Run All. The app generates HDL code for the IP core.
Next, continue to use the HDL Workflow Advisor to generate the software interface model and block library.
Generate Software Interface Model and Block Library
Expand 4. Embedded System Integration. This step integrates the newly generated IP core project into the Zynq SDR reference design, generates the corresponding bitstream, and loads the bitstream onto the board.
Click 4.1. Create Project. In the right pane, click Run This Task. The app creates a project for the embedded system tool.
Click 4.2. Generate Software Interface. In the right pane, click Run This Task. The app generates a software interface library and a template software interface model.
Software Interface Library
The library contains the AXI Interface block generated from the
OFDM HDL subsystem. This block exposes only the AXI-lite control ports but not the data ports. The data ports are present on the transmitter and receiver blocks corresponding to your hardware selected in 1.1. Set Target Device and Synthesis Tool. The data ports of the transmitter and receiver blocks represent the streaming data interface between the FPGA user logic and ARM processor.
When using the library blocks in a downstream model, you must configure the parameters correctly for your application. Take into account that any updates to the
OFDM HDL subsystem are automatically propagated to the library blocks in the downstream model when you run 4.2. Generate Software Interface again.
Template Software Interface Model
You can use the generated template software interface model as a starting point for full SW targeting, for example, in external mode simulation or full deployment. Because HDL Workflow Advisor overwrites the generated model each time you run 4.2. Generate Software Interface, consider saving the generated model under a unique name and develop your software algorithm in the newly saved model.
Generate and Load Bitstream
The last steps of the HDL Workflow Advisor generate a bitstream for the PL and download the bitstream onto the board.
Click 4.3. Build FPGA Bitstream. In the right pane, click Run This Task. The app generates a bitstream for the PL. You can execute this step in an external shell by selecting Run build process externally. This selection allows you to continue using MATLAB while building the FPGA image. After the basic project checks complete, the app marks this check with a green checkmark. However, you must wait until the external shell displays a successful bitstream build before moving on to the next step.
Click 4.4. Program Target Device. In the right pane, click Run This Task. The app downloads the bitstream onto the device. Before continuing with this step, call the
zynqfunction to ensure that MATLAB has the correct physical IP address for the radio hardware:
>> devzynq = zynq('linux','192.168.3.2','root','root','/tmp');
By default, the physical IP address of the radio hardware is
192.168.3.2. If you alter the radio hardware IP address during the hardware setup process, you must supply that address instead.
Alternatively, if you want to load the bitstream outside the HDL Workflow Advisor, create a SDR radio object by using sdrdev object and use the downloadImage function. The type of object you create depends on the Target platform setting in the 1.1. Set Target Device and Synthesis Tool pane.
If the selected radio platform is
ADI RF SOM,
ZC706 and FMCOMMS2/3/4, or
ZCU102 and FMCOMMS2/3/4, create an AD936x radio object.
>> radio = sdrdev('AD936x');
If the selected radio platform is
ZC706 and FMCOMMS5, create an FMCOMMS5 radio object.
>> radio = sdrdev('FMCOMMS5');
Download the bitstream using the radio object interfacing the selected radio device.
>> downloadImage(radio,'FPGAImage', ... 'hdl_prj\vivado_ip_prj\vivado_prj.runs\impl_1\system_top.bit') % Path to the generated bitstream
Software Interface Model
The software interface model is based on the generated template software interface model. The model displays the status information: number of frames synchronized, estimated CFO, decoded header information modulation type and code rate, number of header and data CRC pass and failures, number of bits received, and number of bit errors from the OFDM receiver. The model also plots the real time Data or Header Constellation Diagram based on the headerView control signal.
To open the software interface model, click open model.
The model is configured for the
Xilinx Zynq-7000 Based Board target. You can use this target for the ADI RF SOM or ZC706 and FMCOMMS2/3/4/5 radio platforms. For the ZCU102 and FMCOMMS2/3/4 radio platform, you must reconfigure the model by selecting
Zynq UltraScale+ MPSoC ZCU102 IIO Radio in Model Settings (Ctrl+E) > Hardware Implementation > Hardware board or by double-clicking Select Hardware Board Target.
Run on Zynq Board
To deploy the PL logic, run the step 4.4. Program Target Device in HDL Workflow Advisor.
Click Monitor & Tune to generate and deploy the PS logic on the board connected to Simulink. You can control the configuration from the Simulink model. Alternatively, click Build Deploy & Start to generate and deploy the PS logic on the board disconnected from Simulink. you can use the board as a standalone system independent of host system.
Host Interface Model
In Monitor & Tune mode, the ARM sends the OFDM Receiver output data and receiver status signals back to the host over the Ethernet link by using UDP Send blocks. The IP address of the UDP Send block must be the IP address of the host, by default, '192.168.3.1'. If you alter the IP address during the hardware setup process, you must supply that address instead.
This host interface model, which runs on the host, illustrates how to receive data from the hardware platform and how to postprocess it.
To open the host interface model, click open model.
When the host interface model runs successfully, the model displays the receiver status signals information from the FPGA.
To see the constellation plot, double-click on the Control Scope. By default the software interface model sets modType to
16-QAM, headerView to
false and enableInternalLoopback to
This figure shows the constellation plot when enableInternalLoopback is set to
When the model is running on hardware, changing the enableInternalLoopback port results in distorted constellation plot and status information. To switch between loopback modes, stop the simulation and toggle the enableInternalLoopback port to select the desired mode.
To see the header constellation plot, set headerView to
This example demonstrated the deployment of an OFDM-based transmit and receive algorithm on an SDR platform using the HW/SW co-design work flow. In this example, you can use a variety of modulation schemes and code rates to transmit and receive data over the air.