This example shows how to deploy an orthogonal frequency division multiplexing (OFDM) transmit and receive algorithm. The example combines the HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples into a hardware-software (HW/SW) co-design implementation targeted on the Analog Devices AD9361/AD9364 radio platform.
For a list of supported radio hardware platforms, see Hardware Support. Due to limited hardware resources, this example does not support Avnet ZedBoard and FMCOMMS2/3/4.
This example deploys an OFDM-based transmit and receive algorithm HW/SW co-design implementation targeted on the Analog Devices AD9361/AD9364 radio platform. This example is one of a related set of examples, which show the workflow for designing and deploying an OFDM-based transmit and receive algorithm to hardware. This figure shows the conceptual overview of the example.
The HDL OFDM Transmitter and HDL OFDM Receiver performs all the high-speed signal processing tasks, making the OFDM-based transmit and receive algorithm well suited for FPGA implementation on the programmable logic (PL) of the radio platform. To implement this algorithm on the PL, the example uses the Simulink® hardware models from the HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples as model references. The example is also equipped with an internal channel to apply carrier frequency offset (CFO) and an HDL AWGN channel from HDL Implementation of AWGN Generator (Wireless HDL Toolbox). Control signals
snrdB are provided to tune the channel.
The normalization and denormalization of CFO involves division and multiplication, which operates at low rate. This characteristics makes the CFO computation well suited for software implementation on the integrated ARM® processing system (PS) of the radio platform.
To work with the HW/SW co-design workflow, you must install and configure additional support packages and third-party tools. For more information, see Installation for Hardware-Software Co-Design.
This Simulink model is a hardware generation model of the OFDM-based transmit and receive algorithm for targeting SDR platforms. From this model, you can generate HDL code for the PL and generate a template software interface model using HDL Workflow Advisor. Using the template software interface model, you can generate an application that runs on the PS. This diagram shows the hardware subsystem and a simple test harness.
The OFDM HDL subsystem contains the functionality to be implemented on the PL. ARM processor pulls the status signals information from the FPGA and displays the information on the host.
The OFDM HDL subsystem is an enhanced version of the OFDM Transmitter and OFDM Receiver back to back modelling from the HDL OFDM MATLAB References (Wireless HDL Toolbox) and adds additional functionality to integrate the model with the Zynq® hardware architecture.
The functionality implemented on the PL is in two sections: OFDM Transmit and Receive and Status Signal Generation. The OFDM Transmit and Receive section includes OFDM Tx Channel OFDM Rx, Prepare Inputs, and a Prepare Outputs subsystem.
The OFDM Tx Channel OFDM Rx subsystem includes OFDM Tx, OFDM Rx, Channel Control, and a Payload Data subsystem.
The OFDM Tx implemented from the HDL OFDM Transmitter (Wireless HDL Toolbox) example.
The OFDM Rx implemented from the HDL OFDM Receiver (Wireless HDL Toolbox) example.
The Channel Control subsystem has White Gaussian Noise Generator and Apply CFO subsystems. The White Gaussian Noise Generator has a AWGNGenerator from the HDL Implementation of AWGN Generator (Wireless HDL Toolbox) example. Apply CFO subsystem performs the CFO insertion using the NCO HDL Optimized block.
The Payload data subsystem has an LUT, which stores the data bits used for transmitter waveform generation.
Simulate Hardware Generation Model
To confirm its operation, you can run the hardware generation model using
dataBits stored in the
zynqRadioHWSWOFDMTransmitBits.mat file. The model callback initialization loads the
dataBits to the workspace. To access the callback initialization, select MODELING > Model Settings > Model Properties > Callbacks > InitFcn.
As the model contains a large number of HDL-optimized blocks, which require simulation using sample-based signals, the simulation may take while. Once the simulation has started double click on Control Scope to see the Tx Filtered Spectrum, Header Constellation, and Data Constellation plots.
To enable the AWGN channel between the OFDM Transmitter and Receiver, set
true. The channel can be controlled using the channel impairments
enableInternalLoopback is set to
false, the OFDM signals are transmitted and received externally through the Tx and Rx antennas, where the channel impairments are added over the air in real time.
When the simulation behaviour of the hardware subsystem is satisfactory, you can start the process of generating the HDL IP core, integrating it with the SDR reference design, and generating software for the ARM processor.
Start the targeting workflow by right-clicking the OFDM HDL subsystem and selecting HDL Code > HDL Workflow Advisor.
In Step 1.1, select the
IP Core Generation workflow and the appropriate Zynq radio platform:
ADI RF SOM,
ZC706 and FMCOMMS2/3/4,
ZCU102 and FMCOMMS2/3/4, or
ZC706 and FMCOMMS5. Due to limited hardware resources, this example does not support ZedBoard and FMCOMMS2/3/4.
In Step 1.2, select the
Receive and Transmit path reference design. For this example, you can use default reference design parameters.
In Step 1.3, the interface table maps the DUT signals to the interface signals available in the reference design. Because this example uses a single channel, configure the channel 1 connections and AXI register interfaces as shown in these images.
In Step 1.4, set the DUT synthesis frequency. The DUT synthesis frequency depends on the baseband sampling rate of the system. The OFDM algorithm implementation in this example is built for a sampling rate value of 61.44 MHz.
Step 2 prepares the model for HDL code generation by performing design checks.
Step 3 generates HDL code for the IP core.
Step 4 of the HDL Workflow Advisor integrates the newly generated IP core into the Zynq SDR reference design, generates the corresponding bitstream, and loads the bitstream onto the board.
Step 4.2 generates a software interface library and a template software interface model.
Software Interface Library
The library contains the AXI Interface block generated from the
OFDM HDL subsystem. Note that this block exposes only the AXI-lite control ports but not the data ports. The data ports are present on the transmitter and receiver blocks corresponding to your hardware selected in Step 1.1. The data ports of the transmitter and receiver blocks represent the streaming data interface between the FPGA user logic and ARM processor.
When using the library blocks in a downstream model, you must configure the parameters correctly for your application. Take into account that any updates to the
OFDM HDL subsystem are automatically propagated to the library blocks in the downstream model when you run Step 4.2 again.
Template Software Interface Model
You can use the generated template software interface model as a starting point for full SW targeting, for example, in external mode simulation or full deployment. Because HDL Workflow Advisor overwrites the generated model each time you run Step 4.2, consider saving the generated model under a unique name and develop your software algorithm there.
The last steps of the HDL Workflow Advisor generate a bitstream for the PL and download the bitstream onto the board.
Step 4.3 generates a bitstream for the PL. You can execute this step in an external shell by selecting Run build process externally. This selection allows you to continue using MATLAB while building the FPGA image. Once some basic project checks are complete, Step 4.3 is marked with a green checkmark. However, you must wait until the external shell displays a successful bitstream build before moving on to the next step.
Step 4.4 downloads the bitstream onto the device. Before continuing with this step, make sure that MATLAB is set up with the correct physical IP address of the radio hardware by calling the
>> devzynq = zynq('linux','192.168.3.2','root','root','/tmp');
By default, the physical IP address of the radio hardware is 192.168.3.2. If you alter the radio hardware IP address during the hardware setup process, you must supply that address instead.
Alternatively, if you want to load the bitstream outside HDL Workflow Advisor, create an SDR radio object and use the
downloadImage function. The radio object to create depends on the radio platform selected in Step 1.1.
If the selected radio platform is either
ADI RF SOM,
ZC706 and FMCOMMS2/3/4, or
ZCU102 and FMCOMMS2/3/4, create an AD936x radio object.
>> radio = sdrdev('AD936x');
If the selected radio platform is
ZC706 and FMCOMMS5, create an FMCOMMS5 radio object.
>> radio = sdrdev('FMCOMMS5');
Download the bitstream using the radio object interfacing the selected radio device.
>> downloadImage(radio,'FPGAImage', ... 'hdl_prj\vivado_ip_prj\vivado_prj.runs\impl_1\system_top.bit') % Path to the generated bitstream
The software interface model is based on the generated template software interface model. The model displays the status information:
number of frames synchronized,
estimated CFO, decoded header information
number of header and data CRC pass and failures,
number of bits received, and
number of bit errors from the OFDM receiver. The model also plots the real time Data or Header Constellation Diagram based on the
headerView control signal.
The model is configured for the
Xilinx Zynq-7000 Based Board target. You can use this target for the
ADI RF SOM or
ZC706 and FMCOMMS2/3/4/5 radio platforms. For the
ZCU102 and FMCOMMS2/3/4 radio platform, you must reconfigure the model by selecting
Zynq UltraScale+ MPSoC ZCU102 IIO Radio in Model Settings (Ctrl+E) > Hardware Implementation > Hardware board or by double clicking the provided
Select Hardware Board Target block.
You can run the OFDM software interface model in
Monitor & Tune mode. In this mode, you can control the configuration from the Simulink model. Alternatively, to deploy the design on the board disconnected from Simulink, click
Build Deploy & Start.
Host Interface Model
The ARM sends the OFDM Receiver output data and receiver status signals directly back to the host over the Ethernet link by using UDP send blocks. The IP address of the UDP send block must be the IP address of the host, by default, '192.168.3.1'. If you alter the IP address during the hardware setup process, you should supply that address instead.
This interface model, which runs on the host, illustrates how to receive data from the hardware platform and how to postprocess it.
When the host interface model successfully runs, the model displays the receiver status signals information from the FPGA.
To see the constellation plot, double click on the Control Scope block. By default the software interface model sets
modType constant block as
headerView constant block as
enableInternalLoopback constant block as
This figure shows constellation plot when
enableInternalLoopback constant block is set to
When the model is running on hardware, changing the
enableInternalLoopback status results in distorted constellation plot and status information. To switch between loopback modes, stop the simulation and toggle the
enableInternalLoopback constant block to select the desired mode.
To see the header constellation plot, set
headerView constant block as
This example shows how to implement an OFDM-based transmit and receive algorithm deployed as a HW/SW co-design implementation targeted for SDR. The OFDM implementation transmits and receives data over the air with different modulation types and coderates.