When a digital staircase signal is being fed to the input of a Digital-to-Analog Converter (DAC) on a target board, sinusoidal output may be observed to be superimposed on the staircase signal.
This could be because of the following reason: The DAC is set to a particular frequency (say 8KHz), but the input signal coming into the DAC has a different sample rate (say 1KHz). In the DAC driver implementation, a ping-pong buffering scheme is used where the signal buffer sent to DAC is switched at a frequency to which the DAC is set. If the sample rate of the input signal coming into the DAC (1 KHz) does not match that frequency (8 KHz), one of the ping-pong buffers will contain past-samples or invalid data that will be seen at the output.
In order to resolve this issue, perform one of the following steps:
1. Put the staircase generator and the DAC block into a DSP/BIOS task. This will automatically synchronize the input data rate to that of the DAC. This method is illustrated in the attached model staircase1.mdl
2. Match the sample rate of the signal generator to that of the DAC. This is illustrated in the attached model staircase2.mdl
Note that, in both cases the input signal has been modified to produce a 200Hz repeating sequence as intended in the customer's model "lab4_3.mdl" and the DAC frequency is set to 8KHz. In both cases, the signal observed in the scope matches the sequence except that the DC level is zero. This is because DAC is AC-coupled to line out.
