XADC in System Generator/Model Composer for MATLAB
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SUHANYA M S on 11 Oct 2022
Commented: SUHANYA M S on 12 Oct 2022
I have designed and simulated my entire control logic (using Xilinx blockset of System Generator-Model Composer for MATLAB) and tested in Simulink environment.
Now I need to emulate the ADC register access and controls for the four-channel XADC and set the pin names, etc. How to program/emulate/ design code for XADCs on 7 series FPGA (I use the Nexys A7 board - Artix 7 100t processor) using Xilinx blockset?
I have no experience with programming in Verilog/VHDL. I generate HDL code using System Generator and then generate bitstream and program hardware in Vivado 2020.2.
There are no resources anywhere for XADC emulation / programming using Xilinx blockset. Please help.
I did see some pages where verilog or vhdl files are written and loaded into a black box in Simulink. But I didn't understand it or how it works.
Kiran Kintali on 11 Oct 2022
Can you share your Simulink model?
Are you trying to utilize HDL Coder workflow advisor IP core generation features?
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