Designing bus signals with same names but different buses
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Hello all,
I have a simulink block with two buses which have a signal with the same name.
AB_c.x1, HJ_k.x1.
I would like to make the signals x1 and x1 as an input to the block. Does anybody know how this can be done?
Thanks in advance.
Cheers, Rashmi
3 Comments
ES
on 3 Aug 2017
You can directly connect the selected signal to a subsystem. It has no harm. See above, signal x is connected to 'a'.
If you definitely need the names to match (for naming convention reasons etc) you can rename the signal by putting a passive block (like gain block above) and change the name.
Answers (2)
ES
on 3 Aug 2017
You should use bus selector to select the members you need and take it to subsystem with simple inports (non-bus).
0 Comments
ES
on 3 Aug 2017
You can directly connect the selected signal to a subsystem. It has no harm. See above, signal x is connected to 'a'.
If you definitely need the names to match (for naming convention reasons etc) you can rename the signal by putting a passive block (like gain block above) and change the name.
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