conversion of subsystem to reference model, and merge block port sizing

I have a subsystem I would like to convert to a reference model. The subsystem compiles in external mode without problems within a larger system. When I attempt to convert this subsystem to a reference model, the Conversion Advisor starts complaining about unequal port widths through merge blocks despite the fact that these merge blocks have the "Allow unequal port widths" box checked.

How do I fix this? My system requires variable width data.

[Randy]

Sorry, I should add that this is in R2017A.

[Nick Choi]

Could you provide a minimized reproduction model? It would be helpful to see what is happening within the model.

[Randy]

I believe the root problem is that while merge blocks do support unequal widths, they don't support variable size signals passing through them.