How to set input and output data types separately for a filter when using generatehdl()?

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I am trying to do PDM to PCM conversion on the FPGA and found a couple of nice examples how to generate a CIC+fir-filter with MATLAB. My problem is that an input signal is 1 bit wide but output should be 24 bits (or 16). Generatehdl() function only has an argument for input data type. Is there a way to generate a filter in VHDL with different in and out data types?

Answers (2)

Julia Antoniou
Julia Antoniou on 27 Oct 2017
Hi Johannes,
On the "generatehdl" documentation page, there is a long list of Name-Value pair arguments under the Input Arguments section. One of these Name-Value pairs is 'OutputType'. For VHDL, you can choose to set the OutputType to 'Same as input data type', 'std_logic_vector', and 'signed/unsigned'. See the documentation page linked below:
If this property is not quite what you are looking for, the link below has a list of all the properties that can be changed when using the Filter Design HDL Coder.
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Johannes Oksanen
Johannes Oksanen on 31 Oct 2017
Edited: Walter Roberson on 2 Nov 2017
Thans for your advice! Now I have a better understanding about this case.
However, there is no "OutputDataType", right? What I am trying to do is 1 bit PDM - > 24 (or can be 16) bits PCM conversion with decimation by factor 64. I am following this example and trying to modify it a bit.
So, I like to do something like this but I am facing errors...
inT = numeric(1,1,1);
outT = numeric(1,24,8);
generatehdl(cicCompCascade,'InputDataType', inT, 'OutputType', outT....);
Maybe I should use either std_logic_vector as an input or numeric(1,2,1) and -1/1 PDM instead of 0/1...

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Bharath Venkataraman
Bharath Venkataraman on 2 Nov 2017
The output of cicCompCascade is the output of the filter, and this is what Filter Design HDL Coder uses as the output type. Please make sure that the output of cicCompCascade is 16 or 24 bits and Filter Design HDL Coder will generate the HDL code output type appropriately.

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