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How to set Stateflow transition time for HDL generation

I need to read I2C data with a Zynq-7000 FPGA (MiniZed board) and followed this useful example: IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip.

With an oscilloscope I'm now measuring that SCL signal is 787KHz (wathever is the setting for model sample time in the solver) and I need to take it down to 100KHz.

Just for the sake of testing I tried Temporal Logics on the transitions:

after(5,usec)

but got a diagnostic error:

Cannot use absolute time temporal logic when coding for HDL target

Fair enough, I didn't fancy the idea of using those in the implementation.

My question:

What is the way to set the sample time so that is compatible with HDL code generation?

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1 Answer

Answer by Stefano Orsolini on 10 Aug 2018
Edited by Stefano Orsolini on 10 Aug 2018
 Accepted Answer

I figured!

In the Workflow Advisor section 3.1.2 - Advanced Options the clock setting "Oversampling factor" could be set (from the default 64) to 1 and measure my SCL reach 50MHz. Then setting this factor to 500 my SCL runs at 100KHz.

Weird though... "Oversampling" factor :-D

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