How to configure a correct Duration value in "External Mode Ctrl Panel -> Configure Trigger Options"
1 view (last 30 days)
I am working with the Zedboard. My SIMULINK model is split in PS-PL:
- The main and parts is done in PL, it receives data in input (AXI Stream slave), writes them to the external DDR (AXI MM Master), read them back from the DDR (AXI MM Master), send data to the output (AXI Stream master)
- The PS parts stream data in and receive data out (source and sink)
The source data is an image. I create several version of the PL parts using the HDL workflow advisor for different frame sizes:
When I run the Arm Interface Model in "External Mode", the simulation works fine with the frame size 128x128 and 256x256 using the default setting of the External Mode Panel.
In the other case (512x512 and 1024x1024) the simulation with default external mode setting did not start, the Host (Simulink) was not able to send or receive the data to/from the target (zedboard) for the following reason:
zynq> cat /tmp/aximaster_arm_2.elf.log
Error in UploadLogInfoInit(). Most likely a memory
allocation error or an attempt to re-initialize the
signal selection during the data logging process
(i.e., multiple EXT_SELECT_SIGNAL packets were received
before the logging session terminated or an
EXT_CANCEL_LOGGING packet was received)
** starting the model **
I have reduced the DURATION value in the "Simulink->Code->ExternalModelPanel->TriggerOptions" from default value (1000) to
- 400 for (512x512 size)
- 10 for (1024x1024 size)
The real questions:
1) What is the limitation of the extenal mode in terms of memory and bandwidth trasmission on TCP-IP
2) What is the relationship between
- FPGA clock frequency of the generate IP core
- Sample rate of the Arm Model Interface (that I am using to run the simulation in external mode), its value now is 0.1
- Trigger DURATION value ?
It is not clear to me which guide,way I should use to set the DURATION vale.
Any feedback or answers are accepted.