Unable to use JTAG and 'aximaster' to read/write memory in FPGA KC705 Evaluation Board.

Hi *,

Firstly, let me give you some information about the HW and SW I am using:

• Matlab R2018a
• Vivado 2018.2.2
• Kintex KC705 evaluation board.
• Digilent Utilities v2.2.1 (re-installed in case of missing when vivado was installed)
• Digilent System v2.12.1 (re-installed in case of missing when vivado was installated)

Secondly, as my target is to read/write memory on FPGA using Matlab all the information I am using comes from the next examples (I am using part of them):

• https://de.mathworks.com/help/supportpkg/xilinxfpgaboards/examples/access-fpga-external-memory-using-matlab-as-axi-master.html
• https://de.mathworks.com/help/supportpkg/xilinxfpgaboards/ug/ip-core-generation-workflow-without-an-embedded-arm-processor-xilinx-kintex-7-kc705.html

Then using some of the commands I think are necessary for Matlab implementation, the next error arises:

>> hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2018.2\bin');
Prepending following Xilinx Vivado path(s) to the system path:
C:\Xilinx\Vivado\2018.2\bin
>> filProgramFPGA('Xilinx Vivado','C:\Vivado_projects\MicroBlaze_IP_interface_COMM - Copy\MicroBlaze_IP_interface.runs\impl_1\mb_project_wrapper.bit',1)
### Generating Vivado programming script
### Checking Vivado tool
### Start loading bitstream "C:\Vivado_projects\MicroBlaze_IP_interface_COMM - Copy\MicroBlaze_IP_interface.runs\impl_1\mb_project_wrapper.bit"
### Loading bitstream "C:\Vivado_projects\MicroBlaze_IP_interface_COMM - Copy\MicroBlaze_IP_interface.runs\impl_1\mb_project_wrapper.bit" completed successfully
>> m = aximaster('Xilinx')
Error using fpgadebug_mex
Could not find compatible JTAG AXI master IP.
Make sure that your FPGA board has been programmed correctly.
Also check if the JTAG specific paramters are set correctly if you have more than one device on the JTAG chain.


Error in aximaster/openCable

Error in aximaster

I am not sure if the version (either Vivado or Matlab) have to be in my case and I need to change them for older one.

If you think there might be a problem with my implementation in vivado, I check in Vivado opening the JTAG connection and programming the device and I do see the AXI module programmed.

Is there any other possible way to control FPGA using matlab, or any hint by chance that I am doing something wrong?

If you think some extra information would be useful, please let me know and I will try to complement my point

Thanks in advance for your time.

BR,

Mauricio

[Mir Lodro]

Hello,

Do you have an insight on targeting FPGA of X310 USRPs? I want to implement this on the FPGA of USRPs X310. The FPGA of USRP X310 is Xilinx Kintex 7 -410T. I haven't tried yet, but I am hopeful it should work.

Best wishes

Mir

Answer 1

[Jose Mauricio Suarez Mejia]

Solve it!.

Matlab R2018a does not support Vivado 2018.2. Fortunately there is now available Matlab R2019a which supports that version of vivado and has all the support packages (containing MATLAB to AXI Master IP) to write and read memory from matlab to Kintex KC705 Eva. board in my case.

Cheers!.

[Long Hoang]

Hi

I have inboxed you to ask the solution from you.

Thank you

L.

[Jose Mauricio Suarez Mejia]

Hi Long,

Did you reveived my email?. Please confirm, otherwise to post here.

BR,

Jose Suarez