I'm trying to import this verilog "toy code" but I'm getting an error. (note: this code is just to test the import functionality)
module reduced (
input wire clk,
input wire reset,
output wire [15 :0] status
reg [6:0] output_read_addr=0; // the address at which we will read resulting samples
reg [15:0] output_read_data; // the data that has been retrieved from memory
reg [15:0] output_storage[0:127]; // this memory is used to store data from the computing algorithm
always @(posedge clk) begin
output_read_data <= output_storage[output_read_addr];
The error I get is:
Signal 'output_read_addr' is not supported in vector index operation.
Hdl Import parse failed.
Any help would be great! Any chance this can work on 19a?