How do you make a Simulink subsystem block that is scalable like a generate statement in VHDL?

Hi,

How do you make a simulink subsystem model that would permit the user to change the number of instantiated blocks similar to a generate statement in vhdl? I am trying to make a subsystem block with a small memory for each lane of a super sample data bus. I want to be able to scale it with the super sample paramenter (ie. SSR=4 make 4 parallel memories, SSR-8 would make 8 parallel memories). Any help is appreciated.