I have a Data Aquisition Module written in VHDL and inserted into Simulink via a DocBlock Blackbox Subsystem.(Matlab 2018a)
The blackbox outputs data at a low samplerate of 20kHz(And uses the FPGAs 50Mhz clock internally). It has a Latency of 750 clock cycles(50 Mhz clock) from aquisition trigger(which is supposed to be the 20kHz Clock Enable with Phase 0) to output. The data processing path afterwards runs at 20kHz with an oversampling factor of 2500.
My Problem: The Blackbox sample time in Simulink is configured at the low(20KHz) sample time. I want to process the data in the same 20 Khz period that it is aquired(but with a 750 cycle delay in oversampling cycles). But the Implementation Latency Parameter in HDLBlockProperties refers to the blocks sampling time(So 750 refers to 750x20kHz periods instead of 750x50Mhz periods).
Changing the Blackbox Sample Time to 50Mhz and using a Downsample(or Rate Transition) with a 750 cycle Sample Offset doesnt work either, because they both enforce maximum delay when used with the HDLCoder. (The Data is only available at the start of the next 20Khz cycle)
Is there a way to declare the Oversampling Pipeline depth of a Blackbox Implementation that I am missing? (So that the clock rate pipeline optimisations know about the 750 cycles for its pipeline budget)
The Picture shows the wanted behaviour.
Since I want to synchronize the data with other data aquired at the start of a 20KHz cycle, I can't move the aquisition point 750 cycles before the clock enable.
Thank you very much for your time.