Implementation Latency of Blackbox Subsystem when using oversampling

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Dominique Görner
Dominique Görner on 10 May 2020
Answered: Kiran Kintali on 10 Jun 2020
I have a Data Aquisition Module written in VHDL and inserted into Simulink via a DocBlock Blackbox Subsystem.(Matlab 2018a)
The blackbox outputs data at a low samplerate of 20kHz(And uses the FPGAs 50Mhz clock internally). It has a Latency of 750 clock cycles(50 Mhz clock) from aquisition trigger(which is supposed to be the 20kHz Clock Enable with Phase 0) to output. The data processing path afterwards runs at 20kHz with an oversampling factor of 2500.
My Problem: The Blackbox sample time in Simulink is configured at the low(20KHz) sample time. I want to process the data in the same 20 Khz period that it is aquired(but with a 750 cycle delay in oversampling cycles). But the Implementation Latency Parameter in HDLBlockProperties refers to the blocks sampling time(So 750 refers to 750x20kHz periods instead of 750x50Mhz periods).
Changing the Blackbox Sample Time to 50Mhz and using a Downsample(or Rate Transition) with a 750 cycle Sample Offset doesnt work either, because they both enforce maximum delay when used with the HDLCoder. (The Data is only available at the start of the next 20Khz cycle)
Is there a way to declare the Oversampling Pipeline depth of a Blackbox Implementation that I am missing? (So that the clock rate pipeline optimisations know about the 750 cycles for its pipeline budget)
The Picture shows the wanted behaviour.
Since I want to synchronize the data with other data aquired at the start of a 20KHz cycle, I can't move the aquisition point 750 cycles before the clock enable.
Thank you very much for your time.
  1 Comment
Dominique Görner
Dominique Görner on 19 May 2020
As I understand it, the easiest way to allow this, is to allow disabling "enforce maximum delay" on downsample blocks. And then treating them as a block with the offset as an internal pipeline depth(indexed from the start of the slower rate), for use in Pipeline optimisation. This wouldn't allow Blackbox modules being used in the middle of a pipeline, but at least at the beginning, where external/blackbox IPs are more common.
The more ideal Solution would be to add a "Pipeline Latency" property to Blackbox subsystems, in order to include them anywhere in the chain. Or reference the Implementation Latency to the base(oversampling) clock.
This is of course just an outside view with now understanding of the inner workings and limitations of HDLCoder.

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Answers (3)

Kiran Kintali
Kiran Kintali on 10 May 2020
Hi Dominque,
Is it possible to share a mockup model with the basic configuration of doc block based blackbox as you describe and corresponding upsample and downsample blocks?
This will help provide additional guidance based on the model sample time and oversampling requirements.
Thanks
  2 Comments
Dominique Görner
Dominique Görner on 9 Jun 2020
So can i expect anything more here? This is sadly turning out to be a major bottleneck for my thesis.

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Kiran Kintali
Kiran Kintali on 10 Jun 2020
With HDLCoder we have done a very detailed Fied-Oriented Controller model on FPGA/SoC. See the attached document.
Happy to share more details and implementation models. Feel free to contact us support@mathworks.com
Thanks

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