Cannot Validate Phase Locked Loop on F28069M Launchpad

Hello everyone,

Currently Im testing my power electronics generated code. In order to assess it, Im breaking the model and testing part by part. Now Im testing the PLL, so in order to test it, I generate the code for the PLL embedded on a 30KHz ADC interrupt. Inside the interrupt, I process the PLL and send the data through UART and catch the data on another simulink model and display it on a scope.

The PLL model has been simulated on simulink with expected results, however once I generate the code and deploy into the MCU, it doesnt match the simulation. Im attaching the model for reference.

Any help will be appreciated.

Thanks,

Rolando

[Joel Van Sickel]

Hello Rolando,

I can't easily see something wrong with the code, but here are a few things to consider.

1, are you sure the PLL is running at the rate you want it to run at?

2: if you are using the support package, you don't need to explicitly use the uart to capture data, you can connect simulink directly to the controller.

3: there will be noise on the ADC, could the noise explain what you are seeing.

4: can you take the data captured by the adc and stream it into your simulink model to see if you are getting the data that you thyink you are?

Regards,

Joel

[Rolando Aguilera]

Hello Joel,

Thanks for the help, regarding your questions:

1. Yes PLL is triggered at 30KHz, same as PWM frequency.
2. Yes, I have tried External Mode, but the data seen on the scope is corrupted due to the high speed of the interrupt, hence using UART module.
3. Im not reading any ADC channel instead, Im using a Look up table with a counter to simulate ideal ADC conditions after scaling
4. I can try that, but If you see the model Im simulating it with a Look up table (in order to have ideal sine inputs)

One note is that the clarke transform performs well (I have sent the data through UART and the scope displays the correct waveform). Other thing that I have notice from debugging in CCS is that the arctan is not computed correctly and still figuring out why. If you have any additional suggestions, let me know.

Thanks,

Rolando

[Rolando Aguilera]

Hello Joel,

Upon endlessly tests I made the PLL worked. What I saw is that code generation has trouble when using "preexisting" blocks as I simulated a synchronous reference frame PLL with a simulink defined integrator vs a custom made one.

Waveform generation can be seen from the UART simulink model attached beforehand or by using CCS debugger graphing window.

Im attaching the model, for someone who might benefit in the future.

Thanks,

Rolando