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When using Simulink Desktop real-time external mode, there is a serious delay and mismatch between the data sent by UDP to the FPGA hardware and the data received by UDP.

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Jingchao Li
Jingchao Li on 20 Jul 2020
Edited: Jingchao Li on 20 Jul 2020
I sent a sine signal to the FPGA hardware through the packet output module, and at the same time the FPGA hardware sent the signal back and received it with the packet input module. There was a large delay and mismatch between the two.How can I fix it?

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