Simulink model for DAC with Jitter noise in CTSD
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I'd like to ask you if someone as an idea to modelize a DAC with Jitter noise in Simulink.
At the moment I'm designing a continuous time sigma delta (CTSD) and I'm using the ZOH block (Zero-Order-Hold block) in the system feedback that works as ideal DAC (digital-to-analog-converter). If it's correct, my idea should be to keep this block and add somenthing at the input port. I attach below what I've found searching but doesn't work, any ideas?
link to the image's page
Thanking you in advance,
Qi Wei ZHAO on 14 Jan 2022
The reason it doesn't work is, your model is for simulating jitter's effect on the sampling switch, which only applies to DT delta-sigma ADC. In CTDS ADC, the way jitter affects circuits is to shift the location of feedback DAC's transition time. This process is not related with finding the derivative of an input signal, which is DT's situation.