Integrate and dump output delay

Hi there, I am trying to build simple modulation schemes in Simulink, with the use of the "Integrate and dump" block at the demodulator. It always shows a one sample delay for the received signal as I clear the "Output intermediate values" box. Is this delay actually a real-life parameter or just a consequence of numerical solver operation in Simulink? I have gone through the documentation but still a bit puzzled on this. I'd much appreciate a reply, thanks.