Problems in converting Matlab code to VERILOG (HDL Coder)
4 views (last 30 days)
Show older comments
Hi I have been trying to generate VERILOG code for Automotive Adaptive Cruise control model. I am converting matlab code into verilog code so that I can implement it on FPGA. But the conversion is not possible.
I have some error like this: "Expected R to be one of these types: double. Instead it is of type Embedded.fi"
I do not understand this error completely. Some one please help me out in solving this.
Regards
1 Comment
Kaustubha Govind
on 20 Sep 2013
Perhaps you can also post the snippet of code that the error points to.
Answers (4)
Kiran Kintali
on 20 Sep 2013
Please contact technical support with the MATLAB code.
Most likely you are running into an operation or function which is not supported and needs to be replaced with a LUT or other approximation.
The error message seems to indicate variable 'R' cannot be fi type since it is not supported by Fixed-Point Designer.
0 Comments
Ravikanth
on 21 Sep 2013
3 Comments
Kaustubha Govind
on 26 Sep 2013
Is the type of the variable 'a' double or fi? I don't see that line in the file that you attached.
The message about parallelization seems to suggest that you are attempting to generate code from a PARFOR loop or some other Parallel Computing construct. Such parallelized code produces calls to OpenMP in generated code.
See Also
Products
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!