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Problems in converting Matlab code to VERILOG (HDL Coder)

Asked by Ravikanth on 20 Sep 2013
Latest activity Commented on by Kaustubha Govind on 26 Sep 2013

Hi I have been trying to generate VERILOG code for Automotive Adaptive Cruise control model. I am converting matlab code into verilog code so that I can implement it on FPGA. But the conversion is not possible.

I have some error like this: "Expected R to be one of these types: double. Instead it is of type"

I do not understand this error completely. Some one please help me out in solving this.


  1 Comment

Perhaps you can also post the snippet of code that the error points to.

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4 Answers

Answer by Kiran Kintali on 20 Sep 2013

Please contact technical support with the MATLAB code.

Most likely you are running into an operation or function which is not supported and needs to be replaced with a LUT or other approximation.

The error message seems to indicate variable 'R' cannot be fi type since it is not supported by Fixed-Point Designer.


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Answer by Ravikanth on 21 Sep 2013

Thank you Mr. Kiran. What surprises me is I have not declared any variable R. Now is it a system generated Intermediate variable? I'll anyways post code snippet.


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Answer by Ravikanth on 21 Sep 2013

The attached is source file. Please download.


Ravikanth: What specific line(s) does the error occur at? Does the error message point to a specific part of the code?

"Warning: The specified compiler (lcc) does not support the OpenMP library; turning off parallelization. ??? Attempt to extract field 'ProductMode' from 'double'."

I have some how managed to eliminate that error but now finding new error..but the warning was always present. The so called "Turning off parallelization". what does it mean?? I am able to pass through Fixed point conversions. The problem is at Verification of fixed point code stage. The line in which the error is being occurred is in the fixed point translated file":iskmsb = eml_const(strcmpi(a.ProductMode,'KeepMSB'));".


Is the type of the variable 'a' double or fi? I don't see that line in the file that you attached.

The message about parallelization seems to suggest that you are attempting to generate code from a PARFOR loop or some other Parallel Computing construct. Such parallelized code produces calls to OpenMP in generated code.

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Answer by Ravikanth on 26 Sep 2013

Kaustubha Govind: Got any idea of what ever is happening??


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