Search results: product_base_code:HD - MATLAB Answers

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Results for product_base_code:"HDL Coder" (1,234 results)

Results 1 - 50 of 1,234

1

answer

0 votes
7 views

How to specify device in Matlab for HDL code generation

Asked by Vladislav about 20 hours ago

Latest activity Answered by Vladislav about 18 hours ago

1

answer

0 votes
9 views

How to work with arrays in HDL Coder?

Asked by Dima on 25 Apr 2024 at 17:01

Latest activity Answered by Kiran Kintali on 25 Apr 2024 at 18:31

Code Generation HDL Coder HDL Code Generation from MATLAB Code Generation with Workflow Advisor

0

answers

0 votes
8 views

Error when generating HDL code for deserializer1D

Asked by Luca on 23 Apr 2024 at 16:20

Latest activity Edited by Luca on 25 Apr 2024 at 7:17

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
11 views

HDL Coder Error: HDL code generation does not support variable-size matrix type.

Asked by SHUHENG on 22 Apr 2024 at 10:43

Latest activity Commented on by SHUHENG on 24 Apr 2024 at 6:54

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

0

answers

0 votes
0 views

Using VHDL package files in Simulink

Asked by Cort on 23 Apr 2024 at 17:50

Code Generation HDL Coder

0

answers

0 votes
1 view

How to generate IP block from QAM receiver example?

Asked by Jakub on 23 Apr 2024 at 14:12

Code Generation

1

answer

0 votes
15 views

How to give random inputs for my simulink design?

Asked by Utkarsh on 16 Apr 2024 at 6:18

Latest activity Answered by Kiran Kintali on 21 Apr 2024 at 23:32

Code Generation

1

answer

0 votes
10 views

FPGA Turnkey doesn't update Xilinx Vivado as synthesis tool even after setting tool path

Asked by Shalini on 16 Apr 2024 at 13:56

Latest activity Edited by Kiran Kintali on 21 Apr 2024 at 23:22

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
33 views

MATLAB Function always infers outputs as doubles

Asked by Lucas Ritzdorf on 17 Apr 2024 at 5:02

Latest activity Edited by Kiran Kintali on 21 Apr 2024 at 23:07

Code Generation HDL Coder

1

answer

0 votes
1 view

When I right click on a block using Xilinx System Generator and Simulink, why do I get errors in MATLAB?

Asked by MathWorks Support Team on 1 Feb 2019

Latest activity Edited by MathWorks Support Team on 17 Apr 2024 at 23:50

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

0

answers

0 votes
5 views

FPGA-in-the-Loop(FIL) validation fails when FPGA board is included in the test using board IP address

Asked by Shalini on 16 Apr 2024 at 14:17

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
16 views

How to compare results of two or more simulink models in one?

Asked by Utkarsh on 16 Apr 2024 at 6:54

Latest activity Edited by Manikanta Aditya on 16 Apr 2024 at 7:04

Code Generation HDL Coder

1

answer

0 votes
15 views

Cannot write to AXI-Lite registers [HDL coder, PYNQ, HDL Vision toolbox]

Asked by Anton Wasser on 14 Apr 2024 at 12:27

Latest activity Edited by Kiran Kintali on 15 Apr 2024 at 20:55

FPGA, ASIC, and SoC Development Vision HDL Toolbox HDL Code Generation and Deployment

1

answer

0 votes
81 views

Implementing logarithmic function via Simulink HDL Coder

Asked by Eirik Nordeng on 21 Mar 2024

Latest activity Commented on by Kiran Kintali on 12 Apr 2024 at 1:19

2

answers

1 vote
20 views

Dynamic LUT in HDL coder

Asked by Philipp on 16 Oct 2023

Latest activity Commented on by Philipp on 9 Apr 2024 at 11:00

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

1

answer

0 votes
39 views

How to set Unconditional Transition State for Else Statement in HDL Coder with a Counter?

Asked by Michael Felger on 2 Apr 2024 at 8:54

Latest activity Edited by Michael Felger on 4 Apr 2024 at 11:36

Accepted Answer by Tom Richter

Simulink Applications General Applications

0

answers

0 votes
11 views

Code Frequency Calculation for the GPS HDL Acquisition and Tracking Using C/A Code Example

Asked by Kaan on 3 Apr 2024 at 17:54

Code Generation

1

answer

0 votes
7 views

can we use HDL coder for functions that have another functions inside themselve ??

Asked by fahim GH on 3 Jun 2015

Latest activity Moved by DGM on 2 Apr 2024 at 19:09

Code Generation HDL Coder

1

answer

0 votes
46 views

How can HDL Code Generation for a full system be performed with System Composer Model that contains multiple Simulink models?

Asked by Brad Williams on 20 Mar 2024

Latest activity Commented on by Brad Williams on 2 Apr 2024 at 13:22

Accepted Answer by Kiran Kintali

Systems Engineering System Composer

0

answers

0 votes
46 views

ZEDBOARD UART-USB matlab setup on linux

Asked by rohith gopakumar on 1 Apr 2024 at 8:39

Latest activity Edited by rohith gopakumar on 1 Apr 2024 at 15:31

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
4 views

Vivado project creation or IP Core generation fails with "Project name is illegal" error

Asked by MathWorks Support Team on 24 Jan 2022

Latest activity Edited by MathWorks Support Team on 31 Mar 2024 at 21:21

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
1 view

How can I view the default TCL file for the HDL Workflow Advisor Step 4.3 Build FPGA Bitstream?

Asked by MathWorks Support Team on 24 Jul 2019

Latest activity Edited by MathWorks Support Team on 31 Mar 2024 at 21:10

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
15 views

How do you generate HDL code for the Artix-7 family of boards? What is the recommended workflow for this?

Asked by MathWorks Support Team on 7 Jun 2022

Latest activity Edited by MathWorks Support Team on 31 Mar 2024 at 21:07

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
30 views

Are Digilent Zybo boards supported for the Zynq workflow with HDL Coder & Embedded Coder?

Asked by MathWorks Support Team on 20 Apr 2022

Latest activity Edited by MathWorks Support Team on 31 Mar 2024 at 21:07

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
40 views

Confused between Hardware to perform Inference

Asked by Aditya on 24 Mar 2024

Latest activity Answered by Kiran Kintali on 24 Mar 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
3 views

Good FPGA for learning MATLAB for signal processing and comm

Asked by N/A on 19 Mar 2024

Latest activity Commented on by N/A on 20 Mar 2024

Accepted Answer by Tom Richter

FPGA, ASIC, and SoC Development

1

answer

0 votes
10 views

How can I generate IP core for xilinx spartan 6 fpga in matlab

Asked by naren on 19 Mar 2024

Latest activity Answered by naren on 19 Mar 2024

Code Generation

0

answers

0 votes
2 views

Unable to continue running my application on rebooting Xilinx Zynq Ultrascale RFSoC after deploying in "Build, Load and Run" mode.

Asked by Shahzad Anwar Khan on 28 Feb 2024

Latest activity Commented on by Hussain Ali on 18 Mar 2024

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
5 views

Loop based error while performing HDL conversion using HDL workflow

Asked by Siddarth S on 9 Mar 2024

Latest activity Edited by Kiran Kintali on 16 Mar 2024

FPGA, ASIC, and SoC Development Vision HDL Toolbox HDL Code Generation and Deployment

0

answers

0 votes
46 views

how to use vitis with mathwork image

Asked by Raz Elimelech on 14 Mar 2024

Code Generation

1

answer

0 votes
16 views

HDL Coder support for Quartus Prime 23.1

Asked by Lucas Ritzdorf on 11 Mar 2024

Latest activity Commented on by Lucas Ritzdorf on 12 Mar 2024

Code Generation

1

answer

0 votes
3 views

HDL Coder compatibility issue with Libero SoC 2023.2

Asked by Pronadeep Bora on 8 Mar 2024

Latest activity Answered by Kiran Kintali on 12 Mar 2024

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
4 views

Documenting ports in a Simulink fixed point model

Asked by Eirik Nordeng on 11 Mar 2024

Latest activity Edited by madhan ravi on 11 Mar 2024

Accepted Answer by madhan ravi

Code Generation HDL Coder

1

answer

0 votes
2 views

Represent std_logic_vector in Simulink

Asked by Brad Williams on 6 Sep 2023

Latest activity Commented on by Kiran Kintali on 10 Mar 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
6 views

How to modify FPGA-Based Beamforming in Simulink: Algorithm Design

Asked by Nicole Dulieu on 21 Feb 2024

Latest activity Commented on by Nicole Dulieu on 8 Mar 2024

Accepted Answer by George

Radar Phased Array System Toolbox Beamforming and Direction of Arrival Estimation Beamforming

0

answers

0 votes
35 views

ZEDBOARD UART serial port setup error

Asked by EESHWAR MALAVALLI on 6 Mar 2024

Latest activity Edited by EESHWAR MALAVALLI on 6 Mar 2024

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
3 views

Error when using multiple AXI stream interfaces: The specified key is not present in this container

Asked by Alex Alex on 5 Mar 2024

Code Generation

2

answers

0 votes
20 views

Resources utilization for generated HDL code

Asked by Alex Alex on 3 Mar 2024

Latest activity Commented on by Alex Alex on 5 Mar 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

0

answers

0 votes
0 views

HDL Coder bus length interface not appropriate

Asked by Federico Gelmetti on 5 Mar 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

0

answers

0 votes
1 view

How to Transmit a Full Byte in the HW/SW Co-Design QPSK Transmit and Receive Model Using Analog Devices AD9361/AD9364

Asked by Maks on 13 Jan 2024

Latest activity Commented on by Karthik Akula on 5 Mar 2024

Wireless Communications Communications Toolbox PHY Components Modulation QPSK

0

answers

0 votes
10 views

How to find indices of array in hdl coder?

Asked by Siddarth S on 25 Feb 2024

Latest activity Edited by Siddarth S on 5 Mar 2024

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

2

answers

0 votes
4 views

Unable to find the software for XILINXLOGICORE

Asked by Samuel Quiniou on 6 Jan 2020

Latest activity Edited by Stefanie Schwarz on 4 Mar 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
6 views

Do I have to install a third-party synthesis tool to use HDL Coder?

Asked by MathWorks Support Team on 30 Mar 2021

Latest activity Edited by MathWorks Support Team on 4 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

2

answers

0 votes
3 views

IP core generation for built-in Simulink model

Asked by Alex Alex on 6 Feb 2024

Latest activity Edited by Alex Alex on 3 Mar 2024

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

1 vote
601 views

Which versions of Xilinx Vivado are supported with which release of HDL Coder?

Asked by MathWorks Support Team on 16 Apr 2020

Latest activity Edited by MathWorks Support Team on 1 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

2

answers

0 votes
14 views

Error while using HDL coder: variable-size matrix type is not supported for HDL code generation

Asked by Bilal MEJMAA on 7 Jan 2023

Latest activity Commented on by Kiran Kintali on 1 Mar 2024

Accepted Answer by Bilal MEJMAA

Code Generation

1

answer

0 votes
0 views

Why does Loop Streaming not work for my nested loop when generating HDL Code?

Asked by MathWorks Support Team on 9 Oct 2018

Latest activity Edited by MathWorks Support Team on 1 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

1

answer

0 votes
0 views

How do I add multiple AXI4 Master Interfaces to a reference design in HDL Coder?

Asked by MathWorks Support Team on 14 May 2019

Latest activity Edited by MathWorks Support Team on 29 Feb 2024

Accepted Answer by MathWorks Support Team

Simulink Modeling Configure Signals, States, and Parameters Data Types

1

answer

0 votes
6 views

Why do I receive the error "unable to allocate delays to compensate for the N delays introduced by BLOCK in native floating point mode"?

Asked by MathWorks Support Team on 4 Feb 2019

Latest activity Edited by MathWorks Support Team on 29 Feb 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Model and Architecture Design Model Compatibility Checks

1

answer

0 votes
0 views

Using HDL Coder, how can I do partial streaming of a MATLAB loop?

Asked by MathWorks Support Team on 9 Oct 2018

Latest activity Edited by MathWorks Support Team on 29 Feb 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

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