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Results for product_base_code:"HDL Verifier" (209 results)

Results 1 - 50 of 209

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answers

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8 views

Issue in connecting MATLAB and VIVADO

Asked by SHIN DAMIN on 19 Apr 2024 at 6:52

FPGA, ASIC, and SoC Development

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answers

0 votes
5 views

FPGA-in-the-Loop(FIL) validation fails when FPGA board is included in the test using board IP address

Asked by Shalini on 16 Apr 2024 at 14:17

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
3 views

Good FPGA for learning MATLAB for signal processing and comm

Asked by N/A on 19 Mar 2024

Latest activity Commented on by N/A on 20 Mar 2024

Accepted Answer by Tom Richter

FPGA, ASIC, and SoC Development

1

answer

0 votes
9 views

Can you use switches as inputs in a design tested with FPGA-in-the-Loop simulation? (on a Zedboard)

Asked by Julien on 13 Mar 2024

Latest activity Commented on by Julien on 15 Mar 2024

Accepted Answer by Tom Richter

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
8 views

REGARDING CUSTOM FPGA BOARD DEVELOPMENT

Asked by sai kumar morla on 5 May 2017

Latest activity Commented on by Jiaqi Xu on 8 Mar 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
3 views

HDL Verifier, FPGA in the Loop Not detecting Hardware version Information

Asked by Lucky on 17 Feb 2024

Latest activity Answered by Sachin Lodhi on 27 Feb 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
3 views

Is there anyway to test custom IP cores on MATLAB/SIMULINK

Asked by Zhengchen Guo on 24 Feb 2024

Latest activity Commented on by Angela Cuadros Castiblanco on 26 Feb 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
11 views

Results in FPGA-in-loop is different from Vivado simulation and how to debug

Asked by Zhengchen Guo on 22 Feb 2024

Latest activity Answered by YP on 26 Feb 2024

Accepted Answer by YP

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

1

answer

0 votes
11 views

Python code Simulink HDL coder

Asked by Diede Hilhorst on 21 Feb 2024

Latest activity Commented on by Hassaan on 21 Feb 2024

Signal Processing DSP System Toolbox Code Generation HDL Code Generation

2

answers

0 votes
79 views

How to configure Kria KV260 Vision AI Starter Kit for FPGA-in-the-loop with Simulink?

Asked by Fabio on 9 Feb 2024

Latest activity Edited by Fabio on 19 Feb 2024

Code Generation HDL Coder Targeting FPGA & SoC Hardware

3

answers

0 votes
27 views

Issue Connecting to Xilinx FPGA Board for Simulation

Asked by Max on 7 Feb 2023

Latest activity Commented on by YP on 18 Feb 2024

Accepted Answer by YP

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
2 views

HDL Code Generation using remotely installed Vivado

Asked by Fabio on 12 Feb 2024

Latest activity Commented on by Tom Richter on 12 Feb 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
1 view

how to link system generator of xilinx with MATLAB?

Asked by Sivakumaran Chandrasekaran on 30 Dec 2013

Latest activity Commented on by Arima on 25 Jan 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
0 views

Why am I getting a "SD card is read-only" error during hardware setup for HDL Verifier Support Package for Xilinx FPGA Boards?

Asked by MathWorks Support Team on 10 Jan 2024

Latest activity Answered by MathWorks Support Team on 19 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
4 views

How to instance datacapture module into my HDL Code?

Asked by Dongyun Kim on 19 Sep 2023

Latest activity Answered by UDAYA PEDDIRAJU on 15 Jan 2024

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

1

answer

0 votes
27 views

Simulink/HDLVerifier : error setting property 'status' of class 'CosimWizardPkg.CosimWizardDlg'. Value must contain ASCII characters

Asked by Christophe on 10 Jan 2024

Latest activity Commented on by Christophe on 15 Jan 2024

Accepted Answer by Tom Richter

Code Generation HDL Coder

1

answer

0 votes
6 views

FIL I/O options missing in the FIL wizard.

Asked by Charanraj Mohan on 13 Nov 2023

Latest activity Commented on by Charanraj Mohan on 8 Jan 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
8 views

SystemC code generation directly from SIMULINK model

Asked by John Terry on 24 Dec 2023

Latest activity Commented on by Bhanu on 27 Dec 2023

Code Generation HDL Verifier ASIC Testbench Transaction Level Model Generation

1

answer

0 votes
6 views

About Xilinx Vivado ip core, How do I verify ip cores using FPGA-in-the-loop.

Asked by 立杰 on 18 Nov 2023

Latest activity Commented on by 立杰 on 19 Dec 2023

Accepted Answer by Tushar Sharma

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
5 views

How to use hardware mapping with the RFDC Bus creator block for the SOC builder?

Asked by Jim Esmond on 29 Nov 2022

Latest activity Answered by SANKALP DEV on 15 Dec 2023

FPGA, ASIC, and SoC Development SoC Blockset SoC Blockset Supported Hardware Xilinx Devices Hardware I/O Devices

2

answers

0 votes
16 views

Error running simulink with QuestaSim. Failed to connect to server. Make sure loaded HDL simulator library is using shared memory.

Asked by Nicole Dulieu on 6 Dec 2023

Latest activity Answered by Marc Erickson on 6 Dec 2023

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
4 views

FPGA Data Capture speed

Asked by Jiri on 22 Nov 2023

Latest activity Commented on by Jiri on 24 Nov 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
12 views

Is FTDI USB-JTAG supported for FPGA-in-the-Loop (FIL) simulation with HDL Verifier?

Asked by MathWorks Support Team on 26 Oct 2018

Latest activity Edited by MathWorks Support Team on 23 Nov 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

2

answers

0 votes
10 views

I am unable to compile and execute SystemC code generated from a Simulink model

Asked by Advait Thakre on 14 Nov 2023

Latest activity Edited by Jerome Chevalier on 22 Nov 2023

Simulink Modeling Design Model Behavior Multicore Processor Targets

1

answer

0 votes
1 view

Is the Xilinx Platform Cable USB II supported for FIL simulation?

Asked by MathWorks Support Team on 9 May 2019

Latest activity Edited by MathWorks Support Team on 17 Nov 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
20 views

How to setup a JTAG communication between FPGA board and Matlab?

Asked by Daniel Kunz on 22 Nov 2019

Latest activity Commented on by Charanraj Mohan on 13 Nov 2023

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
19 views

Adding Zynq board (xc7z020-2clg400) in 'fpgaBoardManager'.

Asked by Charanraj Mohan on 26 Oct 2023

Latest activity Edited by Charanraj Mohan on 26 Oct 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
14 views

Error: Failed to load shared library "xsim.dir/design/xsimk.so"

Asked by Bilal MEJMAA on 14 Oct 2023

Latest activity Commented on by Bilal MEJMAA on 21 Oct 2023

Code Generation HDL Coder

2

answers

0 votes
1 view

Does MathWorks support the VC707 with HDL Coder & HDL Verifier? If yes, starting at what version of your tools and ending with what version?

Asked by Brian on 6 Oct 2023

Latest activity Answered by Brian on 6 Oct 2023

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
253 views

the 404 error when installing HDL Verifier Support Package for Xilinx FPGA Boards

Asked by 文杰顾 on 6 Sep 2023

Latest activity Commented on by 文杰顾 on 14 Sep 2023

Accepted Answer by Heman P

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
10 views

hdl coder hdl verifier: Error on Test Connection

Asked by Dr. W. Kurt Dobson on 13 Feb 2023

Latest activity Commented on by Heman P on 3 Sep 2023

Code Generation HDL Verifier Verification with FPGA Hardware FPGA-in-the-Loop

0

answers

0 votes
2 views

Cosimulation wizard gives status : Error: Input #2 expected to be a cell array, was double instead.

Asked by Ioannis Andromidas on 12 Aug 2023

Latest activity Commented on by Marc Erickson on 31 Aug 2023

Code Generation Filter Design HDL Coder Code Generation Fundamentals

0

answers

0 votes
1 view

Change the output data type

Asked by Ho on 8 Aug 2023

Latest activity Commented on by Kiran Kintali on 9 Aug 2023

FPGA, ASIC, and SoC Development DSP HDL Toolbox HDL-Optimized Filters and Transforms

1

answer

0 votes
4 views

Offset binary in Simulink HDL

Asked by Ho on 6 Aug 2023

Latest activity Answered by Kiran Kintali on 7 Aug 2023

FPGA, ASIC, and SoC Development

1

answer

0 votes
14 views

AXI manager not working with Vivado 2023.1

Asked by Dan Aronovits on 2 Aug 2023

Latest activity Answered by YP on 4 Aug 2023

Reporting and Database Access MATLAB Report Generator

2

answers

1 vote
43 views

How to resolve a network connection error when downloading support packages?

Asked by MathWorks Support Team on 24 Jan 2013

Latest activity Edited by MathWorks Support Team on 1 Aug 2023

Accepted Answer by MathWorks Support Team

Wireless Communications Communications Toolbox

1

answer

0 votes
0 views

HDL work flow advisor for non evaluation board devices

Asked by Anonymous1 on 11 Apr 2022

Latest activity Answered by Kiran Kintali on 16 Jul 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

8

answers

2 votes
38 views

HDL Verifier and FPGA in the loop

Asked by shreyas on 2 Jun 2012

Latest activity Commented on by Anas EL-FECHTALI on 20 Jun 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
14 views

Issue Connecting to Xilinx FPGA Board for Simulation （Windows ，ZYNQ） Error:Did not receive version information from the hardware.

Asked by 壹王 on 2 Jun 2023

Latest activity Commented on by YP on 6 Jun 2023

Accepted Answer by YP

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

3

answers

0 votes
8 views

filWizard: Error during Validation of Altera Stratix IV GX 230 FPGA development kit

Asked by THOUMY François on 27 Apr 2017

Latest activity Commented on by 壹王 on 2 Jun 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

1 vote
14 views

Why did I receive an error message：ISim engine error: Failed to Load up XSI.

Asked by JHZ on 28 May 2023

Latest activity Edited by Kiran Kintali on 29 May 2023

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
0 views

Why do I get an error complaining that "tmw_esl_vsim_launch.bat" is unrecognized when using the HDL Cosimulation wizard in MATLAB R2016a?

Asked by MathWorks Support Team on 22 Jul 2016

Latest activity Edited by MathWorks Support Team on 4 May 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Verifier Verification with Cosimulation Simulink Cosimulation

1

answer

0 votes
12 views

How to create a custom fpga board to use with IP core generation

Asked by ARNAUD MARTIN on 9 Feb 2023

Latest activity Edited by Kiran Kintali on 13 Feb 2023

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

0

answers

0 votes
0 views

HDL Coder Guided Hardware Setup for HDL Verifier Support Package Xilinx

Asked by Dr. W. Kurt Dobson on 12 Feb 2023

Latest activity Commented on by Dr. W. Kurt Dobson on 12 Feb 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
2 views

I am getting the message "execution of script matlabtb as a function not supported"

Asked by Ashley Scott on 12 Jan 2023

Latest activity Commented on by Ashley Scott on 12 Jan 2023

Accepted Answer by Bora Eryilmaz

Code Generation HDL Verifier Verification with Cosimulation MATLAB Cosimulation

1

answer

0 votes
4 views

"Failed to initialize the RTIOStream library" while installing HDL Verifier Support Package for Xilinx FPGA Boards add-on

Asked by Charles on 9 Dec 2022

Latest activity Commented on by Jestzer on 13 Dec 2022

Accepted Answer by Charles

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
8 views

How i can import an existing IP Core in Vivado in Simulink as block?

Asked by George Lucian Chiriac on 1 Dec 2021

Latest activity Commented on by SUHANYA M S on 1 Dec 2022

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
0 views

How to create or develop an HDL Verifier function for a specific HDL model

Asked by Bilal MEJMAA on 28 Nov 2022

Latest activity Answered by Kiran Kintali on 29 Nov 2022

Accepted Answer by Kiran Kintali

Code Generation HDL Coder

1

answer

0 votes
41 views

Why do I get the error message "Run 'impl_1' has not been launched. Unable to open" when using HDL Coder, HDL Verifier or SoC Blockset?

Asked by MathWorks Support Team on 17 Jun 2019

Latest activity Edited by MathWorks Support Team on 17 Nov 2022

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
1 view

Error using () Data type mismatch at signal 'c_out'.This port expects a Logic data type of size 1

Asked by Deeksha R on 21 Apr 2022

Latest activity Answered by Marc Erickson on 14 Nov 2022

Code Generation HDL Verifier Verification with Cosimulation Simulink Cosimulation

Results 1 - 50 of 209