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HDL Verifier Support Package for Intel FPGA Boards

Debug and test HDL code on Intel FPGAs and SoC FPGAs


Updated 09 Jan 2020

HDL Verifier™ Support Package for Intel® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier and supported Intel FPGA and SoC FPGA boards. With FIL simulation, use MATLAB® or Simulink® to test designs in real hardware for any existing HDL code.
The FPGA Data Capture capability lets you observe signals from your design in MATLAB while the design is running on the Intel FPGA or SoC FPGA. Then use these signals in MATLAB or Simulink for analysis and verification, or view them using the Logic Analyzer in DSP System Toolbox.
The MATLAB as AXI Master IP included in the support package enables you to read from or write to on-board memory locations directly from MATLAB.

Comments and Ratings (3)

wang yuan


Eric Cigan

I got error. Can you check the image?

I installed r2013b with all toolboxes.

MATLAB Release Compatibility
Created with R2014a
Compatible with R2014a to R2019b
Platform Compatibility
Windows macOS Linux