Lane Detection on Simulink Programmable FPGA
Learn how to implement a pixel-stream based lane detection algorithm in Simulink, and deploy it to a Speedgoat Simulink-Programmable FPGA.
Updated 29 Oct 2020
The Speedgoat Lane Detection on FPGA reference application demonstrates the implementation of a lane detection algorithm in Simulink using Vision HDL Toolbox and a Speedgoat Simulink-Programmable FPGA. For a detailed discussion of the workings of the algorithm, please refer to the original Vision HDL example. The differences to the original example include adaptions to work with 1080p image resolution (instead of 480p) and the HDMI interface of the Speedgoat IO333-325k-SFP FPGA module.
Learn How To
- Use Vision HDL Toolbox™ to model a lane detection algorithm in Simulink®
- Auto-generate VHDL code from your Simulink® model and deploy to Speedgoat Simulink Programmable FPGA I/O
- Process high-resolution video streams with high sample frequency in real-time
- Directly access video I/O such as HDMI with low latency
- Open MATLAB and open Simulink Project File
- Click in 'Getting Started' project shortcut
- Follow steps in the documentation