File: ActuatorLoop.vhd

    1   -- -------------------------------------------------------------
    2   -- 
    3   -- File Name: hdl_prj\hdlsrc\ActuatorLoop\ActuatorLoop.vhd
    4   -- Created: 2017-03-23 10:21:11
    5   -- 
    6   -- Generated by MATLAB 9.2 and HDL Coder 3.10
    7   -- 
    8   -- 
    9   -- -------------------------------------------------------------
   10   -- Rate and Clocking Details
   11   -- -------------------------------------------------------------
   12   -- Model base rate: 1e-06
   13   -- Target subsystem base rate: 1e-06
   14   -- 
   15   -- 
   16   -- Clock Enable  Sample Time
   17   -- -------------------------------------------------------------
   18   -- ce_out        1e-06
   19   -- -------------------------------------------------------------
   20   -- 
   21   -- 
   22   -- Output Signal                 Clock Enable  Sample Time
   23   -- -------------------------------------------------------------
   24   -- ActuatorCommand               ce_out        1e-06
   25   -- -------------------------------------------------------------
   26   -- 
   27   -- -------------------------------------------------------------
   28   
   29   
   30   -- -------------------------------------------------------------
   31   -- 
   32   -- Module: ActuatorLoop
   33   -- Source Path: ActuatorLoop
   34   -- Hierarchy Level: 0
   35   -- 
   36   -- Simulink model description for ActuatorLoop:
   37   -- 
   38   -- This model implements a proportional, integral, derivative controller to close the loop on a hydraulic actuator.
   39   -- 
   40   -- Simulink subsystem description for ActuatorLoop:
   41   -- 
   42   -- This model implements a proportional, integral, derivative controller to close the loop on a hydraulic actuator.
   43   -- 
   44   -- -------------------------------------------------------------
   45   LIBRARY IEEE;
   46   USE IEEE.std_logic_1164.ALL;
   47   USE IEEE.numeric_std.ALL;
   48   
   49   ENTITY ActuatorLoop IS
   50     PORT( clk                               :   IN    std_logic;
   51           reset                             :   IN    std_logic;
   52           clk_enable                        :   IN    std_logic;
   53           PositionFeedback                  :   IN    std_logic_vector(31 DOWNTO 0);  -- sfix32_En34
   54           PositionCommand                   :   IN    std_logic_vector(31 DOWNTO 0);  -- sfix32_En34
   55           ce_out                            :   OUT   std_logic;
   56           ActuatorCommand                   :   OUT   std_logic_vector(31 DOWNTO 0)  -- sfix32_En32
   57           );
   58   END ActuatorLoop;
   59   
   60   
   61   ARCHITECTURE rtl OF ActuatorLoop IS
   62   
   63     -- Component Declarations
   64     COMPONENT DiscretePIDController
   65       PORT( clk                             :   IN    std_logic;
   66             reset                           :   IN    std_logic;
   67             enb                             :   IN    std_logic;
   68             u                               :   IN    std_logic_vector(31 DOWNTO 0);  -- sfix32_En33
   69             y                               :   OUT   std_logic_vector(31 DOWNTO 0)  -- sfix32_En32
   70             );
   71     END COMPONENT;
   72   
   73     -- Component Configuration Statements
   74     FOR ALL : DiscretePIDController
   75       USE ENTITY work.DiscretePIDController(rtl);
   76   
   77     -- Signals
   78     SIGNAL PositionCommand_signed           : signed(31 DOWNTO 0);  -- sfix32_En34
   79     SIGNAL PositionFeedback_signed          : signed(31 DOWNTO 0);  -- sfix32_En34
   80     SIGNAL Sum_sub_cast                     : signed(32 DOWNTO 0);  -- sfix33_En34
   81     SIGNAL Sum_sub_cast_1                   : signed(32 DOWNTO 0);  -- sfix33_En34
   82     SIGNAL Sum_sub_temp                     : signed(32 DOWNTO 0);  -- sfix33_En34
   83     SIGNAL Sum_out1                         : signed(31 DOWNTO 0);  -- sfix32_En33
   84     SIGNAL DiscretePIDController_out1       : std_logic_vector(31 DOWNTO 0);  -- ufix32
   85   
   86   BEGIN
   87     -- Model Name: ActuatorLoop
   88     -- Model Version: 1.73
   89     -- Last Modified: 27-Feb-2017 07:21:03
   90     -- 
   91     -- Copyright 2016-2017 The MathWorks, Inc.
   92   
   93     -- <Root>/DiscretePIDController
   94     -- 
   95     -- 
   96     -- Block requirements for <Root>/DiscretePIDController
   97     --  1. HR_3 Hydraulic Actuator Loop Control
   98     u_DiscretePIDController : DiscretePIDController
   99       PORT MAP( clk => clk,
  100                 reset => reset,
  101                 enb => clk_enable,
  102                 u => std_logic_vector(Sum_out1),  -- sfix32_En33
  103                 y => DiscretePIDController_out1  -- sfix32_En32
  104                 );
  105   
  106     PositionCommand_signed <= signed(PositionCommand);
  107   
  108     PositionFeedback_signed <= signed(PositionFeedback);
  109   
  110     -- <Root>/Sum
  111     -- 
  112     -- 
  113     -- Block requirements for <Root>/Sum
  114     --  1. HR_3 Hydraulic Actuator Loop Control
  115     Sum_sub_cast <= resize(PositionCommand_signed, 33);
  116     Sum_sub_cast_1 <= resize(PositionFeedback_signed, 33);
  117     Sum_sub_temp <= Sum_sub_cast - Sum_sub_cast_1;
  118     Sum_out1 <= Sum_sub_temp(32 DOWNTO 1);
  119   
  120     ce_out <= clk_enable;
  121   
  122     ActuatorCommand <= DiscretePIDController_out1;
  123   
  124   END rtl;
  125   
  126