File: DiscretePIDController.vhd

    1   -- -------------------------------------------------------------
    2   -- 
    3   -- File Name: hdl_prj\hdlsrc\ActuatorLoop\DiscretePIDController.vhd
    4   -- Created: 2017-03-23 10:21:11
    5   -- 
    6   -- Generated by MATLAB 9.2 and HDL Coder 3.10
    7   -- 
    8   -- -------------------------------------------------------------
    9   
   10   
   11   -- -------------------------------------------------------------
   12   -- 
   13   -- Module: DiscretePIDController
   14   -- Source Path: ActuatorLoop/DiscretePIDController
   15   -- Hierarchy Level: 1
   16   -- 
   17   -- -------------------------------------------------------------
   18   LIBRARY IEEE;
   19   USE IEEE.std_logic_1164.ALL;
   20   USE IEEE.numeric_std.ALL;
   21   
   22   ENTITY DiscretePIDController IS
   23     PORT( clk                               :   IN    std_logic;
   24           reset                             :   IN    std_logic;
   25           enb                               :   IN    std_logic;
   26           u                                 :   IN    std_logic_vector(31 DOWNTO 0);  -- sfix32_En33
   27           y                                 :   OUT   std_logic_vector(31 DOWNTO 0)  -- sfix32_En32
   28           );
   29   END DiscretePIDController;
   30   
   31   
   32   ARCHITECTURE rtl OF DiscretePIDController IS
   33   
   34     -- Signals
   35     SIGNAL u_signed                         : signed(31 DOWNTO 0);  -- sfix32_En33
   36     SIGNAL Proportional_Gain_mul_temp       : signed(63 DOWNTO 0);  -- sfix64_En65
   37     SIGNAL Proportional_Gain_out1           : signed(31 DOWNTO 0);  -- sfix32_En35
   38     SIGNAL Integral_Gain_mul_temp           : signed(63 DOWNTO 0);  -- sfix64_En62
   39     SIGNAL Integral_Gain_out1               : signed(31 DOWNTO 0);  -- sfix32_En32
   40     SIGNAL Derivative_Gain_mul_temp         : signed(63 DOWNTO 0);  -- sfix64_En72
   41     SIGNAL Derivative_Gain_out1             : signed(31 DOWNTO 0);  -- sfix32_En42
   42     SIGNAL Filter_Coefficient_out1          : signed(31 DOWNTO 0);  -- sfix32_En49
   43     SIGNAL Filter_indtc                     : signed(31 DOWNTO 0);  -- sfix32
   44     SIGNAL gain_mul_temp                    : signed(63 DOWNTO 0);  -- sfix64_En46
   45     SIGNAL Filter_u_gain                    : signed(31 DOWNTO 0);  -- sfix32
   46     SIGNAL Filter_u_dtc                     : signed(31 DOWNTO 0);  -- sfix32_En53
   47     SIGNAL Filter_x_reg                     : signed(31 DOWNTO 0);  -- sfix32_En53
   48     SIGNAL Filter_u_add                     : signed(31 DOWNTO 0);  -- sfix32_En53
   49     SIGNAL SumD_sub_cast                    : signed(43 DOWNTO 0);  -- sfix44_En53
   50     SIGNAL SumD_sub_cast_1                  : signed(43 DOWNTO 0);  -- sfix44_En53
   51     SIGNAL SumD_sub_temp                    : signed(43 DOWNTO 0);  -- sfix44_En53
   52     SIGNAL SumD_out1                        : signed(31 DOWNTO 0);  -- sfix32_En42
   53     SIGNAL Filter_Coefficient_mul_temp      : signed(63 DOWNTO 0);  -- sfix64_En79
   54     SIGNAL Saturate_out1                    : signed(31 DOWNTO 0);  -- sfix32_En32
   55     SIGNAL Sum_out1                         : signed(31 DOWNTO 0);  -- sfix32_En35
   56     SIGNAL SumI2_sub_cast                   : signed(35 DOWNTO 0);  -- sfix36_En35
   57     SIGNAL SumI2_sub_cast_1                 : signed(35 DOWNTO 0);  -- sfix36_En35
   58     SIGNAL SumI2_out1                       : signed(35 DOWNTO 0);  -- sfix36_En35
   59     SIGNAL Kb_out1                          : signed(71 DOWNTO 0);  -- sfix72_En69
   60     SIGNAL SumI1_add_cast                   : signed(31 DOWNTO 0);  -- sfix32_En32
   61     SIGNAL SumI1_out1                       : signed(31 DOWNTO 0);  -- sfix32_En32
   62     SIGNAL Integrator_indtc                 : signed(31 DOWNTO 0);  -- sfix32
   63     SIGNAL gain_mul_temp_1                  : signed(63 DOWNTO 0);  -- sfix64_En46
   64     SIGNAL Integrator_u_gain                : signed(31 DOWNTO 0);  -- sfix32
   65     SIGNAL Integrator_u_dtc                 : signed(31 DOWNTO 0);  -- sfix32_En36
   66     SIGNAL Integrator_x_reg                 : signed(31 DOWNTO 0);  -- sfix32_En36
   67     SIGNAL Integrator_u_add                 : signed(31 DOWNTO 0);  -- sfix32_En36
   68     SIGNAL Sum_add_cast                     : signed(46 DOWNTO 0);  -- sfix47_En49
   69     SIGNAL Sum_add_cast_1                   : signed(46 DOWNTO 0);  -- sfix47_En49
   70     SIGNAL Sum_add_temp                     : signed(46 DOWNTO 0);  -- sfix47_En49
   71     SIGNAL Sum_add_cast_2                   : signed(46 DOWNTO 0);  -- sfix47_En49
   72     SIGNAL Sum_add_temp_1                   : signed(46 DOWNTO 0);  -- sfix47_En49
   73     SIGNAL Sum_out1_dtc                     : signed(31 DOWNTO 0);  -- sfix32_En32
   74   
   75   BEGIN
   76     u_signed <= signed(u);
   77   
   78     -- <S1>/Proportional Gain
   79     Proportional_Gain_mul_temp <= to_signed(1455993913, 32) * u_signed;
   80     Proportional_Gain_out1 <= Proportional_Gain_mul_temp(61 DOWNTO 30);
   81   
   82     -- <S1>/Integral Gain
   83     Integral_Gain_mul_temp <= to_signed(1465657590, 32) * u_signed;
   84     Integral_Gain_out1 <= Integral_Gain_mul_temp(61 DOWNTO 30);
   85   
   86     -- <S1>/Derivative Gain
   87     Derivative_Gain_mul_temp <= to_signed(1495335814, 32) * u_signed;
   88     Derivative_Gain_out1 <= Derivative_Gain_mul_temp(61 DOWNTO 30);
   89   
   90     Filter_indtc <= Filter_Coefficient_out1;
   91   
   92     gain_mul_temp <= to_signed(1125899907, 32) * Filter_indtc;
   93     Filter_u_gain <= resize(gain_mul_temp(63 DOWNTO 46), 32);
   94   
   95     Filter_u_dtc <= Filter_u_gain;
   96   
   97     Filter_u_add <= Filter_x_reg + Filter_u_dtc;
   98   
   99     -- <S1>/Filter
  100     Filter_reg_process : PROCESS (clk, reset)
  101     BEGIN
  102       IF reset = '1' THEN
  103         Filter_x_reg <= to_signed(0, 32);
  104       ELSIF clk'EVENT AND clk = '1' THEN
  105         IF enb = '1' THEN
  106           Filter_x_reg <= Filter_u_add;
  107         END IF;
  108       END IF;
  109     END PROCESS Filter_reg_process;
  110   
  111   
  112     -- <S1>/SumD
  113     SumD_sub_cast <= resize(Derivative_Gain_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 44);
  114     SumD_sub_cast_1 <= resize(Filter_x_reg, 44);
  115     SumD_sub_temp <= SumD_sub_cast - SumD_sub_cast_1;
  116     SumD_out1 <= SumD_sub_temp(42 DOWNTO 11);
  117   
  118     -- <S1>/Filter Coefficient
  119     Filter_Coefficient_mul_temp <= to_signed(1186098168, 32) * SumD_out1;
  120     Filter_Coefficient_out1 <= Filter_Coefficient_mul_temp(61 DOWNTO 30);
  121   
  122     -- <S1>/SumI2
  123     SumI2_sub_cast <= resize(Saturate_out1 & '0' & '0' & '0', 36);
  124     SumI2_sub_cast_1 <= resize(Sum_out1, 36);
  125     SumI2_out1 <= SumI2_sub_cast - SumI2_sub_cast_1;
  126   
  127     -- <S1>/Kb
  128     Kb_out1 <= resize(SumI2_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 72);
  129   
  130     -- <S1>/SumI1
  131     SumI1_add_cast <= Kb_out1(68 DOWNTO 37);
  132     SumI1_out1 <= Integral_Gain_out1 + SumI1_add_cast;
  133   
  134     Integrator_indtc <= SumI1_out1;
  135   
  136     gain_mul_temp_1 <= to_signed(1125899907, 32) * Integrator_indtc;
  137     Integrator_u_gain <= resize(gain_mul_temp_1(63 DOWNTO 46), 32);
  138   
  139     Integrator_u_dtc <= Integrator_u_gain;
  140   
  141     Integrator_u_add <= Integrator_x_reg + Integrator_u_dtc;
  142   
  143     -- <S1>/Integrator
  144     Integrator_reg_process : PROCESS (clk, reset)
  145     BEGIN
  146       IF reset = '1' THEN
  147         Integrator_x_reg <= to_signed(0, 32);
  148       ELSIF clk'EVENT AND clk = '1' THEN
  149         IF enb = '1' THEN
  150           Integrator_x_reg <= Integrator_u_add;
  151         END IF;
  152       END IF;
  153     END PROCESS Integrator_reg_process;
  154   
  155   
  156     -- <S1>/Sum
  157     Sum_add_cast <= resize(Proportional_Gain_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 47);
  158     Sum_add_cast_1 <= resize(Integrator_x_reg & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 47);
  159     Sum_add_temp <= Sum_add_cast + Sum_add_cast_1;
  160     Sum_add_cast_2 <= resize(Filter_Coefficient_out1, 47);
  161     Sum_add_temp_1 <= Sum_add_temp + Sum_add_cast_2;
  162     Sum_out1 <= Sum_add_temp_1(45 DOWNTO 14);
  163   
  164     Sum_out1_dtc <= resize(Sum_out1(31 DOWNTO 3), 32);
  165   
  166     -- <S1>/Saturate
  167     
  168     Saturate_out1 <= to_signed(1288490189, 32) WHEN Sum_out1_dtc > to_signed(1288490189, 32) ELSE
  169         to_signed(-1288490189, 32) WHEN Sum_out1_dtc < to_signed(-1288490189, 32) ELSE
  170         Sum_out1_dtc;
  171   
  172     y <= std_logic_vector(Saturate_out1);
  173   
  174   END rtl;
  175   
  176