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Question
How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?
The dev enviroment of my experiment is Matlab 2020b with Vivavdo 2020. I attached the sysgen model and relative configuration f...
7 months ago | 1 answer | 0
1
answerQuestion
tristate input in hdl verifier?
Hi guys, I met a problem on how to generate tristate bus stimulus in hdl verifier. In details, I need to verify a bus read/writ...
1 year ago | 0 answers | 0
0
answersQuestion
How to update HDL verifier block when VHDL source changes its port definition?
I couldn't find a way to update the block when vhdl source change its source file. So, I have to manually add or remove those de...
1 year ago | 2 answers | 0
2
answersQuestion
Exception on debug C shared library based application when using visual studio 2017
Hello guys, Now, I try and study to use Matlab library compiler to convert matlab script to library function, and call it in C ...
1 year ago | 1 answer | 0
1
answerQuestion
Question on zp2sos gain scaling?
Hello guys, I have a question on matlab zp2sos function. The question is how matlab do scaling when convert z/p/k to zeros...
6 years ago | 0 answers | 0