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Marcin Fisior


Last seen: 4 years ago Active since 2019

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How to generate HDL serial filter architecture form Digital Down-Converter example
Thanks for the replay Unfortunately i have this option greyed out. Any thoughts?

5 years ago | 0

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How to generate HDL serial filter architecture form Digital Down-Converter example
Hi I need to design decimation flter in VHDL so i choose this example of digital down converter. https://www.mathworks.com/hel...

5 years ago | 3 answers | 0

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