Active-HDL™ suite is a comprehensive, integrated for digital IC design and verification that employs hardware description languages and C/C++ solutions. Active-HDL suite has been designed based on customer suggestions and feedback to ensure design productivity and ease-of-use. Active-HDL supports complex FPGA and ASIC designs.
Aldec's HDL-based simulation environment for FPGA and ASIC designs has a built-in interface to the intuitive, technical computing MATLAB® environment.This interface simplifies the verification of hardware design, provides robust visualization and analysis tools, allows extending HDL test benches by using MATLAB code to create complex stimuli, perform UUT data analysis, or visualize simulated data as clearly as possible.
The Simulink® interface in Active-HDL adds the ability to co-simulate mathematical and hardware components of system-level design and gives the flexibility of successive replacement of mathematical models describing the system with target HDL equivalents.
The Simulink diagram can be automatically converted to the format compatible with HDL Coder™ that is an extension available for the Simulink interface.