Campera Electronic Systems ASIP

Campera Electronic Systems ASIPs (Application Specific IP) provide high-performance IP cores for FPGAs, including "off the shelf" high-geared VHDL modules, optimized in terms of speed, power, and resource usage. Campera Electronic Systems (CES) ASIPs are fully functional VHDL modules that implement macro functionalities with super-sample rate techniques, i.e. processing data at a sample rate greater than the FPGA internal clock. CES has developed proprietary HDL design flow, techniques, utilities, and an immense HDL IP cores library with fully verified high-performance building blocks, including two ASIPs libraries: Radar Processing Library and Video Processing Library.

CES has developed a highly configurable, high-performance Radar/Sonar Processing Library that dramatically reduces design and verification time. The library includes: Radar/Sonar Signal Generator, Pulse Compressor with Overlap-Add method, a PFB Channelizer, 2D RX/TX Beamforming, and other typical processing modules capable of processing over 100 GSPS real time continuous data (50GHz instantaneous bandwidth) on a single FPGA with super-sample rate techniques. These ASIP cores are well suited for high-bandwidth applications, Radar/Sonar Emulators, and Electronic Warfare.

The Video Processing Library addresses applications demanding high resolutions (up to 1080p), high frame-rates (up to 150fps) and ultra-low latency. It easily adds competitive advantage to surveillance applications that are subject to movements of the camera or sensor platform. These ASIP cores are especially effective for powerful zoom systems and/or digital video stabilization, object recognition, and tracking systems. The library also contains a vast collection of high performance video/image processing algorithms, such as converters (e.g. RBG to HSV), local filters (e.g. 2D rank/ median filter), geometry transform (e.g. scale), and segmentation and detection (e.g. connected-component labeling).

A MATLAB® user interface (UI) is used to configure the ASIP core and generate a VHDL wrapper for the FPGA implementation/simulation and any other supporting files, such as VHDL stimulus test vectors and floating point reference. A fixed point bit accurate model developed with MATLAB is released with the ASIP core, together with the golden reference floating point model for algorithm exploration and tuning.